Microprocessors/microcomputers : architecture, software, and systems

목차 (Table of Contents)

• CONTENTS
• Section One MICROCOMPUTER ARCHITECTURE = 2
• 1. FUNDAMENTALS OF DIGITAL COMPUTERS = 4
• 1-1 INTRODUCTORY REMARKS = 4
• 1-2 INTRODUCTION TO THE DIGITAL COMPUTER = 5
• 1-2.1 The Typical System = 5
• 1-2.2 The Memory System = 6
• 1-2.3 The Central Processing Unit (CPU) = 7
• 1-2.4 The Input-Output Ports = 8
• 1-3 THE CPU ARCHITECTURE = 8
• 1-3.1 The Functional Subsystems = 8
• 1-3.2 Register and Counters = 9
• 1-3.2.1 The Accumulator = 11
• 1-3.2.2 The Program Counter = 11
• 1-3.2.3 The Instruction Register and Decoder = 12
• 1-3.2.4 The Address Register／Counter = 13
• 1-3.3 The Arithmeitc／Logic Unit (ALU) = 13
• 1-3.4 Timing and Control = 14
• 1-4 THE SEQUENCE OF BASIC OPERATIONS = 14
• 1-4.1 The Basic Timing Sequence = 14
• 1-4.2 Instruction Fetcth／Execution Sequence = 15
• 1-4.3 Data Memory Read Operation = 16
• 1-4.4 Data Memory Write Operation = 16
• 1-4.5 Input-Output Operations = 16
• 14.6 Interrupts = 17
• 1-5 DIGITAL COMPUTER IN BLOCK DIAGRAM FORM = 17
• 1-5.1 Realistic Organization = 17
• 1-5.2 The Microcomputer Organization = 18
• 1-6 THE MICROCOMPUTER STRUCTURE = 20
• 1-7 REVIEW QUESTIONS = 21
• 2. NUMBER SYSTEMS AND BINARY DATA CODING IN MICROCOMPUTERS = 24
• 2-1 BINARY DATA AND NUMBER SYSTEMS = 24
• 2-2 THE PURE BINARY NUMBERS = 27
• 2-2.1 Binary Addition = 28
• 2-2.2 Binary Subtraction in Ones Complement = 30
• 2-2.2.1 The Sign Convention = 30
• 2-2.2.2 The Complement Method = 31
• 2-2.3 Binary Subtraction in Twos Complement = 33
• 2-3 THE OCTAL SYSTEM = 35
• 2-3.1 Why the Octal System? = 35
• 2-3.2 Notation in the Octal System = 35
• 2-3.3 Decimal-to-Octal Conversion = 37
• 2-3.4 Octal-to-Decimal Conversion = 38
• 2-4 THE BINARY-CODED-DECIMAL SYSTEM (BCD) = 39
• 2-4.1 Why the BCD System? = 39
• 2-4.2 Notation in the BCD System = 39
• 2-4.3 Decimal-to-BCD Conversion = 40
• 2-4.4 BCD-to-Pure-Binary Conversion = 40
• 2-4.5 BCD Addition = 42
• 2-4.6 BCD Subtraction = 44
• 2-4.7 Character Representation in BCD = 45
• 2-5 THE HEXADECIMAL SYSTEM = 46
• 2-6 INTERPRETED BINARY DATA = 46
• 2-7 CHARACTER CODES = 47
• 2-8 PROBLEMS AND EXERCISES = 48
• 3. THE MICROPROCESSOR ARCHITECTURE = 50
• 3-1 MICROPROCESSOR INTERNAL BUS STRUCTURES = 50
• 3-1.1 What Are Busses? = 50
• 3-1.2 The Memory Busses = 52
• 3-1.3 The I／O Buses = 55
• 3-1.4 The Memory-I／O Shared Busses = 55
• 3-1.5 Multiplexed Bus System Configuration = 56
• 3-2 THE MACHINE AND INSTRUCTION CYCLES = 58
• 3-2.1 The Clocking System and Sync Pulse = 58
• 3-2.2 The Machine Cycle = 59
• 3-2.3 The Instmction Cycle = 61
• 3-2.3.1 The Fixed Instmction Cycle = 61
• 3-2.3.2 The Vuiable Instruction Cycle = 63
• 3-3 INSTRUCTION FLOW IN THE CPU = 65
• 3-4 DATA FLOW IN THE MICROCOMPUTER = 66
• 3-5 REGISTERS AND COUNTERS = 67
• 3-5.1 General Comments = 67
• 3-5.2 The Stack = 68
• 3-5.2.1 The Cascade Stack = 68
• 3-5.2.2 The Stack Pointer = 70
• 3-5.3 The Status Register = 73
• 3-5.3.1 The Sign Flag = 73
• 3-5.3.2 The Overflow Flag = 73
• 3-5.3.3 The Carry Flag = 76
• 3-5.3.4 The Zero Flag = 77
• 3-5.3.5 The Putty Flag = 77
• 3-5.4General-Purpose Registers (Scratch Pad) = 77
• 3-5.5 Other ALU Registers = 78
• 3-6 REVIEW QUESTIONS = 78
• 3-7 PROBLEMS AND EXERCISES = 80
• 4. MICROPROCESSOR INSTRUCTIONS = 82
• 4-1 WHAT ARE INSTRUCTIONS? = 82
• 4-2 THE INSTRUCTION SET = 85
• 4-2.1 Introductory Remarks = 85
• 4-2.1.1 Categorization by Computer Section = 85
• 4-2.1.2 Categorization by Functions Performed = 86
• 4-2.2 Transfer Data, Arithmetic, and Logic Instructions = 86
• 4-2.2.1 Transfer Data Instmctions = 86
• 4-2.2.2 Arithmetic Instructions = 89
• 4-2.2.3 Logic Instructions = 89
• 4-2.3 Transfer of Control Instructions = 90
• 4-2.3.1 The HALT Instmction = 90
• 4-2.3.2 The JUMP Instmction = 91
• 4-2.3.3 The BRANCH Instruction = 92
• 4-2.3.4 The SKIP Instruction = 93
• 4-2.3.5 The INCREMENT and SKIP IF ZERO (ISZ) Instmction = 94
• 4-2.4 Subroutine Linking Instmctions = 98
• 4-2.5 Operation Instmctions = 98
• 4-2.6 I／O Instmctions = 100
• 4-3 INSTRUCTION ENCODING = 101
• 4-3.1 Machine Language or Machine Codes = 101
• 4-3.2 Mnemonic Codes (Assembly Language) = 101
• 4-3.3 Assemblers and Interpreters = 102
• 4-4 BASIC INSTRUCTION FORMATS = 103
• 4-4.1 Nonmemory Reference Instructions (NMRI) = 103
• 4-4.1.1 Register-to-Register Transfers = 104
• 4-4.1.2 Nontransfer Instmctions = 105
• 4-4.1.3 Multiword NMRI Instmctions = 105
• 4-4.1.4 Multiword Instruction Identification = 106
• 4-4.2 Memory Reference Instruction (MRI) = 107
• 4-5 REVIEW QUESTIONS = 108
• 4-6 PROBLEMS AND EXERCISES = 109
• 5. ADDRESSING MODES IN MICROCOMPUTERS = 112
• 5-1 INTRODUCTORY REMARKS = 112
• 5-2 DIRECT ADDRESSING = 113
• 5-3 INDIRECT ADDRESSING = 114
• 5-3.1 Using Internal CPU Pointers = 114
• 5-3.2 Using Base Page Pointers = 120
• 5-4 PAGE RELATIVE ADDRESSING MODES = 122
• 5-4.1 Current Page Relative Addressing = 122
• 5-4.2 Page 0 Relative Addressing = 125
• 5-4.3 Limitations of the Page Relative Addressing Modes = 126
• 5-5 PROGRAM COUNTER RELATIVE ADDRESSING MODE = 128
• 5-6 IMMEDIATE ADDRESSING = 133
• 5-7 INDEXED ADDRESSING = 133
• 5 7.1 Direct Indexed Addressing = 133
• 5-7.2 Indexed Indirect Addressing (Preindexing) = 137
• 5-7.3 Indirect Indexed Addressing (Postindexing) = 138
• 5-8 OTHER TERMS USED IN ADDRESSING MODES = 141
• 5-9 REVIEW QUESTIONS = 142
• 5-10 PROBLEMS AND EXERCISES = 144
• 6 INSTRUCTION EXECUTION AND MICROSEQUENCES = 148
• 6 1 INTRODUCTORY REMARKS = 148
• 6-2 HOW THE CPU EXECUTES INSTRUCTIONS = 149
• 6-2.1 The Macroinstructions = 149
• 6-2.2 The Microinstmctions = 149
• 6-2.3 The Internal Data Bus = 150
• 6-3 SIMPLE GENERALIZED EXAMPLES OF MICROINSTRUCTIONS = 150
• 6-4 GENERALIZED REALISTIC liP CPU = 157
• 6-4.1 The Scratch-pad Memory = 157
• 6 4.2 The Index Register = 158
• 6-4.3 The Cascade Stack = 158
• 6-4.4 Communicating with the Shared Address Bus = 159
• 6-4.5 Communicating with the Shared Data Bus = 159
• 6-4.6 Realistic Typical KP CPU Block Diagram = 161
• 6-4.7 The Control Unit and Control Signals = 161
• 6-4.7.1 Contml Signals Functions = 161
• 6-4.7.2 Data Transfer Control Logic = 163
• 6-5 MICROPROGRAMMING A ftP CPU = 165
• 6-5.1 The CPU Features and the Block Diagram = 165
• 6-5.2 The Mode Control Signals = 167
• 6-5.3 The ALU Function Initiate Signals = 167
• 6-5.4 The Data Transfer Signals = 168
• 6-6 EXAMPLES OF MICROPROGRAMMING THE LEO lip = 170
• 6-7 THE MICROPROGRAMMABLE MACHINE = 175
• 6-7.1 The Control Memory = 175
• 6-7.2 Advantages and Disadvantages = 176
• 6-7.2.1 Advantages = 176
• 6-7.2.2 Disadvantages = 176
• 6-8 REVIEW QUESTIONS = 177
• 6-9 PROBLEMS AND EXERCISES = 179
• 7. MICROCOMPUTER MEMORIES = 182
• 7-1 INTRODUCTION = 183
• 7-1.1 Microcomputer Memory Philosophy = 183
• 7-1.2 Chip Memories = 183
• 7-2 DEFINITIONS OF MEMORY TYPES = 183
• 7-3 ROMS IN MICROCOMPUTERS = 184
• 7-3.1 ROMs = 185
• 7-3.2 PROMs = 185
• 7-3.3 EPROMs = 186
• 7-3.4 EAROMs = 187
• 7-3.5 The Use of ROMs = 187
• 7-4 ORGANIZATION OF THE PROGRAM MEMORY = 188
• 7-4.1 Introductory Comments = 188
• 7-4.2 Word-Organized ROMs = 188
• 7-4.3 The Address Word = 190
• 7-4.4 The Chip Select Scheme = 190
• 7-5 ORGANIZATION OF THE DATA MEMORY = 192
• 7-5.1 General Comments = 192
• 7-5.2 Bit-Organized RAMs = 194
• 7-6 STANDBY POWER FOR VOLATILE RAMS = 194
• 7-6.1 Power Failure／Retum Operation = 194
• 7-6.2 Typical Power-Fail Sensing Circuit = 195
• 7-7 ADVANCED FEATURES AND CAPABILITIES = 197
• 7-7.1 Bulk Storage on Magnetic Disks = 197
• 7-7.2 Digital Recording on Magnetic Surfaces = 198
• 7-7.2.1 The Retum-to-Zero (RZ) Method = 198
• 7-7.2.2 The Non-Retum-to-Zero (NRZ) Method = 200
• 7-7.3 Floppy Disks = 201
• 7-7.3.1 Tracks on Disks = 203
• 7-7.3.2 Hard-Sectored Disks = 203
• 7-7.3.3 Soft-Sectored Disks = 204
• 7-7.3.4 Recording Density and Storage Capacity = 205
• 7-7.3.5 Access Time = 206
• 7-7.4 Winchester Disks = 208
• 7-7.5 Recent Advances = 209
• 7-8 REVIEW QUESTIONS = 209
• 7-9 PROBLEMS AND EXERCISES = 212
• 8. PARALLEL I／O TRANSFERS PROGRAMMED I／O = 214
• 8-1 DATA TRANSFERS = 214
• 8-2 INTERFACE NETWORK CHIPS = 215
• 8-2.1 The I／O Ports = 215
• 8-2.2 The I／O Device Chips and Port Expansion = 216
• 8-3 WHAT IS PROGRAMMED I／O? = 218
• 8-4 THE DATA TRANSFER SCHEME = 219
• 8-4.1 The Transfer Instruction = 219
• 8-4.1.1 The IOT Instruction Format = 220
• 8-4.1.2 Typical IOT Instmction = 221
• 8-4.2 The Block Diagram of the Programmed I／O Chip = 223
• 8-4.3 The Output Transfer = 224
• 8-4.4 The Input Transfer = 225
• 8-5 UNCONDITIONAL PROGRAMMED I／O TRANSFER = 225
• 8-5.1 General Comments = 225
• 8-5.2 Input Operation = 226
• 8-5.3 Output Operation = 230
• 8-6 CONDITIONAL PROGRAMMED I／O TRANSFER = 231
• 8-6.1 General Remarks = 231
• 8-6.2 The Protocol in Conditional Transfers = 231
• 8-6.3 The Status Check Logic = 233
• 8-7 REVIEW QUESTIONS = 235
• 9. PARALLEL I／O TRANSFERS-INTERRUPT I／O = 238
• 9-1 WHY INTERRUPT I／O? = 239
• 9-2 SEQUENCE OF EVENTS = 239
• 9-3 CPU RESPONSE TO INTERRUPTS = 241
• 9-3.1 Sequence of Events = 241
• 9-3.2 INT REQ Querying Logic = 243
• 9-4 INTERRUPT SERVICE INITIATION = 243
• 9-4.1 Sequence of Events = 243
• 9-4.2 Interrupt Handling Subroutine = 246
• 9-4.3 Branching To Subroutine = 248
• 9-4.3.1 Using BRANCH Instmction = 248
• 9-4.3.2 Using an Address pointer = 250
• 9-4.3.3 Using an Externally Supplied Address = 251
• 9-4.4 Status Saving and Restoring = 252
• 9-4.5 tndentifying the Interrupting Peripheral = 253
• 9-5 THE VECTORED INTERRUPT = 254
• 9-5.1 Introductory Remarks = 254
• 9-5.2 The Sequence of Events = 254
• 9-5.3 Interface Chip Logic = 256
• 9-5.3.1 INT REQ and Peripheral Identification = 256
• 9-5.3.2 Peripheral Selection and Activation = 258
• 9-5.3.3 Data Input Operation = 258
• 9-5.3.4 Data Output Operation = 258
• 9-6 THE SOFTWARE POLLED INTERRUPT = 259
• 9-6.1 Introductory Remarks = 259
• 9-6.2 The Sequence of Event = 259
• 9-6.3 Interrupt Handling Subroutine = 261
• 9-6.4 Polling Operation in the CPU = 263
• 9-6.5 Interface Chip Logic = 265
• 9-7 THE HARDWARE-POLLED INTERRUPT (DAISY CHAIN) = 265
• 9-7.1 The Basic Principle = 265
• 9-7.2 The Logic Diagram = 267
• 9-8 MULTILEVEL PRIORITY INTERRUPTS = 269
• 9-8.1 The Operation = 269
• 9-8.2 Interrupt System Block Diagram = 271
• 9-8.3 Multilevel Priority Interrupt Chip = 272
• 9-9 REVIEW QUESTIONS = 274
• 10. PARALLEL I／O TRANSFERS-DIRECT MEMORY ACCESS = 278
• 10-1 DATA TRANSFERS AND THE TIME ELEMENT = 278
• 10-2 DMA INITIATION = 279
• 10-2.1 Memory Status Indication Mode = 281
• 10-2.2 Cycle Stealing Mode = 282
• 10-3 SINGLE WORD DMA TRANSFER = 282
• 10-3.1 Using Single Auxiliary Memory = 282
• 10-3.2 Using Several Auxiliary Memories = 294
• 10-4 DMA TRANSFER OF SINGLE DATA BLOCK = 284
• 10-4.1 Basic Requirements for Block Transfer Execution = 284
• 10-4.2 Flowchart of DMA BLOCK TRANSFERS = 285
• 10-5 DMA TRANSFER OF SEVERAL DATA BLOCKS = 287
• 10-5.1 The Situation = 287
• 10-5.2 The Flowchart = 288
• 10-6 DMA LOGIC ACTIVATION IN CPU = 288
• 10-6.1 Using CPU Registers = 288
• 10-6.2 CPU Response to DMA REQ Signal = 290
• 10-7 OPERATION OF THE INTERFACE CHIP = 292
• 10-7.1 DMA REQ and Response = 292
• 10-7.2 Auxiliary Memory Lockin = 292
• 10-7.3 Word and Block Count = 294
• 10-7.4 Data Memory Access Address = 294
• 10-7.5 The Transfer Operation of the First Word = 295
• 10-7.6 Data Memory Address Update = 295
• 10-7.7 Word Counter Update = 295
• 10-7.8 Block Counter Update = 295
• 10-7.9 Termination of DMA Operation = 296
• 10-7-10 Decrement and Terminate DMA Logic = 296
• 10-8 ADVANCED FEATURES AND CAPABILITIES = 296
• 10-8.1 Channel Priorities = 296
• 10-8.1.1 Fixed Priorities = 297
• 10-8.1.2 Channel Rotation Priority = 299
• 10-8.2 The DMA-300 Chip = 300
• 10-8.2.1 Operational Features = 300
• 10-8.2.2 The Initialization Bytes = 300
• 10-9 REVIEW QUESTIONS = 305
• 10-10 PROBLEMS AND EXERCISES = 307
• 11. SERIAL I／O TRANSFERS = 308
• 11-1 INTRODUCTION = 308
• 11-2 CONVERSION AND SYNCHRONIZATION LOGIC = 309
• 11-2.1 Block Diagram of Serial I／O = 309
• 11-2.2 Serial／Puallel Conversion = 310
• 11-2.3 Level Normalization = 310
• 11-2.4 Level-to-Bit Conversion and Synchronization = 316
• 11-2.5 Synchronization of Random Input Pulses = 316
• 11-3 DATA IDENTIFICATION IN SERIAL BIT STREAM = 319
• 11-3.1 The Problem = 319
• 11-3.2 Byte Start Identification Method = 320
• 11-3.3 Synchronous and Asynchronous Serial Transmissions = 321
• 11-3.4 Byte Capture Logic for Serial Bit Strem = 322
• 11-4 REVIEW QUESTIONS = 323
• 12. PROGRAMMABLE I／O INTERFACES = 326
• 12-1 WHAT ARE PROGRAMMABLE INTERFACES? = 326
• 12-2 PROGRAMMABLE INTERFACES FOR SERIAL TRANSFERS = 327
• 12-2.1 The UART = 327
• 12-2.1.1 Basic Functions and Features = 327
• 12-2.1.2 Timing and Synchronization = 328
• 12-2.1.3 Baud Rate and Data Rate = 331
• 12-2.1.4 Data Buffering = 333
• 12-2.1.5 UART Error Indications = 336
• 12-2.1.6 UART Initialization = 337
• 12-2.1.7 Commands and Hags = 338
• 12-2.1.8 UART Block Diagram = 339
• 12-2.2 The USART = 341
• 12-3 PROGRAMMABLE INTERFACES FOR PARALLEL TRANSFERS = 342
• 12-3.1 Basic Functions and Features = 342
• 12.3.2 Additional Features and Capabilities = 342
• 12.3.3 The INTEL 8255 Programmable Peripheral Interface (PPI) = 344
• 12-3.3.1 The Block Diagram = 344
• 12-3.3.2 Modes of Operation = 345
• 12-3.3.3 Control Word-Mode Definition = 348
• 12-3.3.4 Control Word-Control Port (Bit-Set／Reset) = 348
• 12-4 REVIEW QUESTIONS = 349
• 12-5 PROBLEMS AND EXERCISES = 351
• 13. DIGITAL-TO-ANALOG AND ANALOG-TO-DIGITAL CONVERTERS = 354
• 13-1 INTRODUCTION = 354
• 13-2 DIGITAL-TO ANALOG CONVERTER = 355
• 13-2.1 Voltage Output DACs = 355
• 13-2.1.1 The Resistor Summing Network = 356
• 13-2.1.2 The Resistor Ladder Networ = 359
• 13-2.1.3 The BCD-Weighted DAC = 360
• 13-2.2 Current Output DAC = 361
• 13-2.3 DAC Operating Parameters = 364
• 13-3 ANALOG-TO-DIGITAL CONVERTERS = 368
• 13-3.1 The Comparator = 368
• 13-3.2 The Ramp-Voltage Method = 368
• 13-3.3 Successive-Approximation Method = 372
• 13-3.3.1 Simple-Counter Method = 372
• 13-3.3.2 The Sequencing Method = 373
• 13-3.4 A／D Converter Operating Parameters = 378
• 13-4 REVIEW QUESTIONS = 379
• 13-5 PROBLEMS AND EXERCISES = 380
• 14. INTERVAL TIMERS AND COUNTERS = 384
• 14-1 INTRODUCTION = 385
• 14-2 COUNTER-TIMER PRINCIPLES = 385
• 14-2.1 The Down Counter = 385
• 14-2.2 The Time Constant Register = 386
• 14 2.3 The Prescalar = 386
• 14-2.4 The Interrupt Feature = 387
• 14-2.5 The Timer Mode = 387
• 14-2.6 The Counter Mode = 387
• 14-3 COUNTER-TIMER CHIP ARCHITECTURE = 388
• 14-3.1 Generalized Block Diagram = 388
• 14-3.1.1 Chip Select and Read Write Signals = 388
• 14-3.1.2 Master Control Register = 389
• 14-3.1.3 Channel Selection and Initialization Logic = 390
• 14-3.1.4. Channel Control Logic = 390
• 14 3.1.5 External Signals to and from Peripherals = 390
• 14-3.1.6 Interrupt to CPU = 390
• 14-3.2 The Initialization Words = 390
• 14-3.2.1 The Channel Control Word = 390
• 14-3.2.2 The Time Constant Word = 391
• 14-3.3 Block Diagram of Channel Control Logic = 392
• 14-4 CHANNEL CONTROL REGISTER FORMAT = 394
• 14-5 CHANNEL SELECTION AND INITIALIZATION PROCESS = 394
• 14-5.1 Writing the Channel Control Word = 394
• 14-5.2 Writing the Time Constant Word = 396
• 14-6 PRESCALE FACTOR SELECTION = 396
• 14-6.1 Prescalar Enable／Disable = 396
• 14-6.2 Prescalar Operation = 398
• 14-7 CONTROL LOGIC FOR SELECTED CHANNEL = 399
• 14-7.1 Counter Mode Operation = 399
• 14-7.2 Timer Mode Operation = 400
• 14-7.3 Down Counter Read-Out = 400
• 14-8 APPLICATIONS OF TIMERS AND COUNTERS = 401
• 14-8.1 Counter Applications = 401
• 14-8.2 Timer Applications = 404
• 14-9 ADVANCED FEATURES AND CAPABILITIES = 408
• 14-9.1 One-Shot with Programmable Pulse Width = 408
• 14-9.1.1 Description of the Chip = 409
• 14-9.1.2 Operational Modes = 409
• 14-9.1.3 The Initialization Words = 410
• 14-9.1.4 The Channel Control Logic for One-Shot Operation = 412
• 14-9.2 Squam-Wave Generation = 417
• 14-9.2.1 The Initialization Words = 417
• 14-9.2.2 Squaw-Wave Generation Operation = 418
• 14-10 REVIEW QUESTIONS = 422
• 14-11 PROBLEMS AND EXERCISES = 424
• Section Two MICROCOMPUTER SYSTEMS = 430
• 15. MICROCOMPUTER TIMING DIAGRAMS = 432
• 15-1 INTRODUCTION = 432
• 15-2 SIGNAL SYMBOLS IN TIMING DIAGRAMS = 433
• 15-3 BUS CONVENTIONS = 434
• 15-4 TRANSITIONS CAUSED BY TRANSITIONS = 435
• 15-5 LEVEL CHANGES CAUSED BY SIGNAL TRANSITIONS = 436
• 15-6 SIGNAL TRANSITIONS CAUSED BY LEVELS = 437
• 15-7 BUS SIGNAL CHANGES CAUSED BY LEVEL CHANGES = 438
• 15-8 LEVEL CHANGES CAUSED BY LEVELS = 438
• 15-9 SINGLE／MULTIPLE TRANSITIONS CAUSED BY SINGLE／MULTIPLE LEVELS = 438
• 15-10 TRANSITIONS CAUSED BY LEVEL／TRANSITION COMBINATIONS = 439
• 15-11 DELAY TIME CONVENTIONS = 440
• 16. MICROPROCESSOR-MEMORY INTERFACES = 444
• 16-1 INTRODUCTION = 445
• 16-2 MEMORY TIMING = 445
• 16-2.1 Instruction Fetch Cycle = 445
• 16-2.2 Data Memory Read Cycles = 448
• 16-2.2.1 Without WAIT States = 448
• 16-2.2.2 With WAIT States = 448
• 16-2.3 Data Memory Write Cycles = 450
• 16-2.3.1 Without WAIT States = 450
• 16-2.3.2 With WAIT States = 450
• 16-3 MEMORY ADDRESS MAPPING = 450
• 16-4 DECODING AND DECODERS = 454
• 16-4.1 Device or Chip Select = 454
• 16-4.2 Nonabsolute Address Decoding = 457
• 16-4.3 Absolute Decoding = 459
• 16-5 CPU-MEMORY INTERFACES = 461
• 16-5.1 Using Decoder Chips = 461
• 16-5.2 Using Logic Gates = 463
• 16-6 REVIEW QUESTIONS = 465
• 16-7 PROBLEMS AND EXERCISES = 466
• 17. MICROPROCESSOR-I／O INTERFACES = 468
• 17-1 INTRODUCTION = 468
• 17-2 MEMORY-MAPPED I／O = 469
• 17-2.1 Single-Bit Mapping = 469
• 17-2.2 Multiple-Bit Mapping = 474
• 17-2.3 Advantages／Disadvantages of Memory-Mapped I／O = 479
• 17-3 ISOLATED I／O = 479
• 17-3.1 Single I／O Chip = 480
• 17-3.2 Multiple I／O Chips = 482
• 17-3.3 Some Unusual Interface Situations = 484
• 17-4 REVIEW QUESTIONS = 486
• 17-5 PROBLEMS AND EXERCISES = 488
• Section Three MICROCOMPUTER SOFTWARE = 490
• 18. INTRODUCTION TO MICROCOMPUTER SOFTWARE = 492
• 18-1 INTRODUCTION = 492
• 18-1.1 What Is Software? = 492
• 18-1.2 Software versus Hardware = 493
• 18-1.3 Areas of Software Activities = 493
• 18-1.4 Software Development Cycle = 493
• 18-2 SYSTEMS SOFTWARE = 496
• 18-2.1 The Machine Language = 497
• 18-2.2 The Assembler = 497
• 18-2.3 The Compiler = 499
• 18-2.4 The Interpreter = 500
• 18-2.5 The Text Editor = 501
• 18-2.6 Loaders = 501
• 18-2.7 Linkage Editors and Library Loaders = 503
• 18-2.8 Testing, Debugging, and Diagnostic Programs = 504
• 18-2.9 Executive Programs = 505
• 18-3 REVIEW QUESTIONS = 505
• 19. PROBLEM DEFINITION AND FLOWCHARTING = 508
• 19-1 PROBLEM STATEMENT = 508
• 19-1.1 The Need = 508
• 19-1.2 An Example = 509
• 19-2 FLOWCHARTS = 512
• 19-2.1 What Is a Flowchart? = 512
• 19-2.2 When Is a Flowchart Prepued? = 512
• 19-2.3 Program Flowchart Symbols = 512
• 19-2.4 Systems Flowchart Symbols = 514
• 19-3 LEVELS OF FLOWCHARTING = 515
• 19-3.1 Concept-Level Flowchart = 515
• 19-3.2 Algorithm-Level Flowchart = 516
• 19-3.3 Instruction-Level Flowchart = 520
• 19-4 PROGRAM LOOPING = 525
• 19-4.1 What Are Iterative Loops? = 525
• 19-4.2 Unconditional Iterative Loops = 525
• 19-4.3 Conditional Iterative Loops = 526
• 19-5 REVIEW QUESTIONS = 530
• 19-6 PROBLEMS AND EXERCISES = 532
• 20. ORGANIZING THE DATA = 536
• 20.1 DATA AND INFORMATION = 536
• 20-1.1 Difference Between Data and Information = 536
• 20-1.2 The ASCII Code = 537
• 20-1.3 Packing and Unpacking Data = 538
• 20-1.4 Multiple Precision Capability = 540
• 20-2 NUMERICAL QUANTITIES IN SCIENTIFIC NOTATION = 541
• 20-2.1 Exponential Notation = 541
• 20-2.2 Sign Convention = 543
• 20-2.3 Floating-point Operations = 544
• 20-3 REVIEW QUESTIONS = 552
• 20-4 PROBLEMS AND EXERCISES = 553
• 21. ORGANIZING THE DATA TRANSFORMATION PROCESS = 556
• 21-1 ORGANIZATION OF DATA STRUCTURES = 556
• 21-1.1 Graphical Representation of Data Stmctures = 556
• 21-1.2 Systematic Organization of Data = 558
• 21-1.2.1 Types and Items = 558
• 21-1.2.2 Arrays = 559
• 21-1.2.3 Lists = 565
• 21-1.2.4 Data Structures and Memory Requirements = 568
• 21-2 FUNDAMENTAL FUNCTIONAL STATEMENTS = 571
• 21-3 THE PROBLEM DEFINITION PROCESS = 572
• 21-3.1 Generalized Statements = 572
• 21-3.1.1 Single-Pass Stmcture = 572
• 21-3.1.2 Iterative Loops Stmcture = 573
• 21-3.2 Using Subroutines = 575
• 21-3.3 Miscellaneous Statements = 578
• 21-4 REVIEW QUESTIONS = 579
• 21-5 PROBLEMS AND EXERCISES = 580
• 22. INTRODUCTION TO ASSEMBLERS AND INTERPRETERS = 582
• 22-1 INTRODUCTION TO ASSEMBLY LANGUAGE = 583
• 22-1.1 Process of Program Assembling = 583
• 22-1.2 Problems in Anual Assembly = 584
• 22-2 THE ASSEMBLER PROGRAM = 584
• 22-2.1 The Objectives = 585
• 22-2.2 The Translation Process = 585
• 22-2.3 Assembly Language Syntax = 586
• 22-2.3.1 Statement Structure = 587
• 22-2.3.2 Label Field = 587
• 22-2.3.3 Operation Code Field = 587
• 22-2.3.4 Argument Field = 587
• 22-2.3.5 Comment Field = 588
• 22-2.3.6 Field Identification = 588
• 22-2.4 Assembly Language Directives (Pseudo-operations) = 589
• 22-2.5 Symbol Tables or Dictionaries = 591
• 22-2.5.1 Fixed Tables = 591
• 22-2.5.2 Dynamic Tables = 592
• 22-2.6 Macro Assembler = 592
• 22-3 MECHANICS OF ASSEMBLER OPERATION = 595
• 22-3.1 Single-Pass Assembler = 595
• 22-3.2 Two-Pass Assembler = 596
• 22-3.3 Resident or Self-Assemblers = 596
• 22-3.4 Nonresident Assemblers = 597
• 22-3.5 Cross-Assemblers = 597
• 22-4 THEINTERPRETER = 597
• 22-4.1 What is an Interpreter? = 597
• 22-4.2 Advantages of Interpreters = 598
• 22-4.3 Shortcomings of Interpreters = 599
• 22-5 THE "BASIC" INTERPRETER = 599
• 22-5.1 File Manipulation Commands = 599
• 22-5.2 Line Editing Commands = 600
• 22-6 REVIEW QUESTIONS = 602
• 23. OPERATING SYSTEMS AND SYSTEMS SOFTWARE = 604
• 23-1 OPERATING THE COMPUTING SYSTEM = 605
• 23-1.1 Manual or Stand-Alone System = 605
• 23-1.2 Systems Softwue = 605
• 23-2 OPERATING SYSTEMS = 606
• 23-2.1 What Are Operating Systems? = 606
• 23-2.2 Advantages and Shortcomings = 606
• 23-3 PRINCIPAL TASKS PERFORMED BY OSs = 607
• 23-3.1 The Program Deve pment Tas = 607
• 23-3.2 The Job Control Task = 608
• 23-3.2.1 Basic Batch Processing = 608
• 23-3.2.2 Queued Sequential Batch Processing = 609
• 23-3.2.3 Priority Queued Batch Processing = 610
• 23-3.3 The Data Control Task = 610
• 23-4 SYSTEMS SOFTWARE = 611
• 23-4.1 What Are Operating Systems? = 611
• 23-4.1.1 Monitors and Supervisory Systems = 611
• 23-4.1.2 Resident Loader = 611
• 23-4.1.3 Servicing I／O Transfers = 612
• 23-4.1.4 Examining and Altering Memory Cells = 613
• 23-4.1.5 Logical Addresses for I／O Devices = 613
• 23-4.1.6 Trap Subroutines = 614
• 23-4.1.7 Program Status Word (PSW) Display = 614
• 23-4.1.8 Task Priority and Scheduling = 614
• 23-4.1.9 Operator-Machine Communications = 615
• 23-4.1.10 Timekeeping Functions = 615
• 23-4.1.11 Memory Protection／Security = 615
• 23-4.2 Utility Programs = 616
• 23-4.2.1 Code Conversion Programs = 616
• 23-4.2.2 Sorting and Merging Programs = 616
• 23-4.2.3 Copy Programs = 617
• 23-4.2.4 Text Editors = 617
• 23-5 RESIDENT OPERATING SYSTEMS = 617
• 23-5.1 Main-Memory-Resident OS = 618
• 23-5.2 Disk-Resident OS = 618
• 23-5.3 Tape-Resident OS = 618
• 23-7 REVIEW QUESTIONS = 619
• APPENDICES = 623
• A. THE ASCII CHARACTER SET AND CODES = 624
• B. SYSTEM TESTING, CHECKOUT,AND VALIDATION = 626
• B-1 PROBLEMS OF MICROCOMPUTER SYSTE@ TESTING = 626
• B-2 MICROCOMPUTER TESTING APPROACHES = 627
• B-2.1 Computer Simulation = 627
• B-2.1.1 Description = 627
• B-2.1.2 Advantages = 628
• B-2.1.3 Disadvantages = 628
• B-2.2 Signature Testing = 628
• B-2.2.1 Description = 628
• B-2.2.2 Advantages = 628
• B-2.2.3 Disadvantages = 629
• B-2.3 Pattern Recogni = 629
• B-2.3.1 Description = 629
• B-2.3.2 Fixed Pattern Generation Procedure = 630
• B-2.3.3 The Test Procedure = 631
• B-2.3.4 Advantages = 632
• B-2.3.5 Disadvantages = 632
• B-2.4 Pattern Generation = 633
• B-2.4.1 Description = 633
• B-2.4.2 Advantages = 633
• B-2.4.3 Disadvantages = 633
• C. THE LOGIC ANALYZER = 635
• C-1 WHAT IS A LOGIC ANALYZER? = 635
• C-2 TYPICAL LOGIC ANALYZER BLOCK DIAGRAM = 636
• C-2.1 Data Acquisition Function = 636
• C-2.1.1 Sampling Modes = 638
• C-2.1.2 Latch Mode = 639
• C-2.2 Triggering Function = 640
• C-2.3 Storage Function = 643
• C-2.4 Display Function = 644
• D. HEYADECIMAL ADDITION AND SUBTRACTION = 645
• D-1 HEXADECIMAL ADDITION = 645
• D-2 HEXADECIMAL SUBTRACTION = 647
• GLOSSARY = 649
• INDEX = 667