<P>A 10-bit 40-MS/s analog-to-digital converter (ADC) that is suitable for wireless access in vehicular environment applications is introduced. In order to satisfy the severe requirement of a wide range operating temperature under the given cons...
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https://www.riss.kr/link?id=A107669888
2014
-
SCOPUS,SCIE
학술저널
6-10(5쪽)
0
상세조회0
다운로드다국어 초록 (Multilingual Abstract)
<P>A 10-bit 40-MS/s analog-to-digital converter (ADC) that is suitable for wireless access in vehicular environment applications is introduced. In order to satisfy the severe requirement of a wide range operating temperature under the given cons...
<P>A 10-bit 40-MS/s analog-to-digital converter (ADC) that is suitable for wireless access in vehicular environment applications is introduced. In order to satisfy the severe requirement of a wide range operating temperature under the given constraints, the ADC was simplified by eliminating nonessential building blocks such as reference drivers, a sample-and-hold amplifier (SHA), and level shifters. The proposed internal signal amplification method extends the effective signal range in both multiplying digital-to-analog converter and flash ADC, as well as the error correction range. A new clock generation circuit for a SHA-less pipelined ADC removes the need for a higher frequency external clock. The prototype ADC was fabricated in a 180-nm CMOS process. The ADC core consumes 23.4 mW at 3.3-V/1.8-V supplies. The measured worst differential nonlinearity and integral nonlinearity were -0.52/+0.7 LSB and -0.86/ +0.9 LSB, respectively, at a temperature of -40 <SUP>°</SUP> C. The signal-to-noise-and-distortion ratio stayed above 55 dB in the Nyquist condition in a temperature range of -40 <SUP>°</SUP>C-125 <SUP>°</SUP>C, which is about a 0.5 effective-number-of-bits drop from the room-temperature result.</P>
Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector