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      KCI등재 SCI SCIE SCOPUS

      Data Randomization Scheme for Endurance Enhancement and Interference Mitigation of Multilevel Flash Memory Devices

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      https://www.riss.kr/link?id=A103380306

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      다국어 초록 (Multilingual Abstract) kakao i 다국어 번역

      In this letter, we propose a data randomization scheme for endurance and interference mitigation of deeply-scaled multilevel flash memory. We address the relationships between data patterns and the raw bit error rate. An on-chip pseudorandom generator composed of an address-based seed location decoder is developed and evaluated with respect to uniformity. Experiments performed with 2x-nm and 4x-nm NAND flash memory devices illustrate the effectiveness of our scheme. The results show that the error rate is reduced up to 86% compared to that of a conventional cycling scheme. Accordingly, the endurance phenomenon can be mitigated through analysis of interference that causes tech shrinkage.
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      In this letter, we propose a data randomization scheme for endurance and interference mitigation of deeply-scaled multilevel flash memory. We address the relationships between data patterns and the raw bit error rate. An on-chip pseudorandom generator...

      In this letter, we propose a data randomization scheme for endurance and interference mitigation of deeply-scaled multilevel flash memory. We address the relationships between data patterns and the raw bit error rate. An on-chip pseudorandom generator composed of an address-based seed location decoder is developed and evaluated with respect to uniformity. Experiments performed with 2x-nm and 4x-nm NAND flash memory devices illustrate the effectiveness of our scheme. The results show that the error rate is reduced up to 86% compared to that of a conventional cycling scheme. Accordingly, the endurance phenomenon can be mitigated through analysis of interference that causes tech shrinkage.

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      참고문헌 (Reference)

      1 W. Lee, "Soild State Disk and Input/Output Method"

      2 H. Shiga, "Nonvolatile Semiconductor Memory and Data Reading Method"

      3 J. Cha, "New Fault Detection Algorithm for Multi-level Cell Flash Memories" 341-356, 2011

      4 R.L. Galbraith, "Method and Apparatus for Randomizing Data in a Direct Access Storage Device"

      5 R. Bez, "Introduction to Flash Memory" 91 (91): 489-502, 2003

      6 R. Micheloni, "Inside NAND Flash Memories" Springer 2010

      7 T.-H. Chen, "An Adaptive-Rate Error Correction Scheme for NAND Flash Memory" 53-58, 2009

      8 K. Park, "A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories" 919-928, 2008

      9 Heesung Lee, "A Symbiotic Evolutionary Design of Error-Correcting Code with Minimal Power Consumption" 한국전자통신연구원 30 (30): 799-806, 2008

      10 C. Lee, "A 32-Gb MLC NAND-Flash Memory with Vth Endurance-Enhancing Schemes in 32nm CMOS" 46 (46): 97-106, 2011

      1 W. Lee, "Soild State Disk and Input/Output Method"

      2 H. Shiga, "Nonvolatile Semiconductor Memory and Data Reading Method"

      3 J. Cha, "New Fault Detection Algorithm for Multi-level Cell Flash Memories" 341-356, 2011

      4 R.L. Galbraith, "Method and Apparatus for Randomizing Data in a Direct Access Storage Device"

      5 R. Bez, "Introduction to Flash Memory" 91 (91): 489-502, 2003

      6 R. Micheloni, "Inside NAND Flash Memories" Springer 2010

      7 T.-H. Chen, "An Adaptive-Rate Error Correction Scheme for NAND Flash Memory" 53-58, 2009

      8 K. Park, "A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories" 919-928, 2008

      9 Heesung Lee, "A Symbiotic Evolutionary Design of Error-Correcting Code with Minimal Power Consumption" 한국전자통신연구원 30 (30): 799-806, 2008

      10 C. Lee, "A 32-Gb MLC NAND-Flash Memory with Vth Endurance-Enhancing Schemes in 32nm CMOS" 46 (46): 97-106, 2011

      11 K.-D Suh, "A 3.3 V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme" 128-129, 1995

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      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2023 평가예정 해외DB학술지평가 신청대상 (해외등재 학술지 평가)
      2020-01-01 평가 등재학술지 유지 (해외등재 학술지 평가) KCI등재
      2005-09-27 학술지등록 한글명 : ETRI Journal
      외국어명 : ETRI Journal
      KCI등재
      2003-01-01 평가 SCI 등재 (신규평가) KCI등재
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      학술지 인용정보

      학술지 인용정보
      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.78 0.28 0.57
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.47 0.42 0.4 0.06
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