1 W. Lee, "Soild State Disk and Input/Output Method"
2 H. Shiga, "Nonvolatile Semiconductor Memory and Data Reading Method"
3 J. Cha, "New Fault Detection Algorithm for Multi-level Cell Flash Memories" 341-356, 2011
4 R.L. Galbraith, "Method and Apparatus for Randomizing Data in a Direct Access Storage Device"
5 R. Bez, "Introduction to Flash Memory" 91 (91): 489-502, 2003
6 R. Micheloni, "Inside NAND Flash Memories" Springer 2010
7 T.-H. Chen, "An Adaptive-Rate Error Correction Scheme for NAND Flash Memory" 53-58, 2009
8 K. Park, "A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories" 919-928, 2008
9 Heesung Lee, "A Symbiotic Evolutionary Design of Error-Correcting Code with Minimal Power Consumption" 한국전자통신연구원 30 (30): 799-806, 2008
10 C. Lee, "A 32-Gb MLC NAND-Flash Memory with Vth Endurance-Enhancing Schemes in 32nm CMOS" 46 (46): 97-106, 2011
1 W. Lee, "Soild State Disk and Input/Output Method"
2 H. Shiga, "Nonvolatile Semiconductor Memory and Data Reading Method"
3 J. Cha, "New Fault Detection Algorithm for Multi-level Cell Flash Memories" 341-356, 2011
4 R.L. Galbraith, "Method and Apparatus for Randomizing Data in a Direct Access Storage Device"
5 R. Bez, "Introduction to Flash Memory" 91 (91): 489-502, 2003
6 R. Micheloni, "Inside NAND Flash Memories" Springer 2010
7 T.-H. Chen, "An Adaptive-Rate Error Correction Scheme for NAND Flash Memory" 53-58, 2009
8 K. Park, "A Zeroing Cell-to-Cell Interference Page Architecture with Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories" 919-928, 2008
9 Heesung Lee, "A Symbiotic Evolutionary Design of Error-Correcting Code with Minimal Power Consumption" 한국전자통신연구원 30 (30): 799-806, 2008
10 C. Lee, "A 32-Gb MLC NAND-Flash Memory with Vth Endurance-Enhancing Schemes in 32nm CMOS" 46 (46): 97-106, 2011
11 K.-D Suh, "A 3.3 V 32Mb NAND Flash Memory with Incremental Step Pulse Programming Scheme" 128-129, 1995