1 J. Lee, "Wire Optimization for Multimedia SoC and SiP Designs" 55 (55): 2202-2215, 2008
2 J. Sparsø, "Principles of Asynchronous Circuit Design: A System Perspective" Kluwer Academic Publishers 2001
3 T. Seceleanu, "On-chip Segmented Bus: A Self-Timed Approach" 216-221, 2002
4 E.-J. Choi, "New Data Encoding Method with a Multi-value Logic for Low Power Asynchronous Circuit Design" 4-, 2006
5 C.A. Zeferino, "Models for Communication Tradeoffs on System-on-Chip" 394-, 2002
6 T. Takahashi, "Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-valued Current Signal Multiplexing" E89-C (E89-C): 1598-1604, 2006
7 E. Nigussie, "High-Speed Completion Detection for Current Sensing On-chip Interconnects" 45 (45): 547-548, 2009
8 E. Nigussie, "High Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling" 13-, 2007
9 J. Kim, "Exploiting New Interconnect Technologies in On-chip Communication" 2 (2): 124-136, 2012
10 M.E. Dean, "Efficient Self-Timing with Level-Encoded 2-Phase Dual-Rail (LEDR)" 55-70, 1991
1 J. Lee, "Wire Optimization for Multimedia SoC and SiP Designs" 55 (55): 2202-2215, 2008
2 J. Sparsø, "Principles of Asynchronous Circuit Design: A System Perspective" Kluwer Academic Publishers 2001
3 T. Seceleanu, "On-chip Segmented Bus: A Self-Timed Approach" 216-221, 2002
4 E.-J. Choi, "New Data Encoding Method with a Multi-value Logic for Low Power Asynchronous Circuit Design" 4-, 2006
5 C.A. Zeferino, "Models for Communication Tradeoffs on System-on-Chip" 394-, 2002
6 T. Takahashi, "Implementation of a High-Speed Asynchronous Data-Transfer Chip Based on Multiple-valued Current Signal Multiplexing" E89-C (E89-C): 1598-1604, 2006
7 E. Nigussie, "High-Speed Completion Detection for Current Sensing On-chip Interconnects" 45 (45): 547-548, 2009
8 E. Nigussie, "High Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling" 13-, 2007
9 J. Kim, "Exploiting New Interconnect Technologies in On-chip Communication" 2 (2): 124-136, 2012
10 M.E. Dean, "Efficient Self-Timing with Level-Encoded 2-Phase Dual-Rail (LEDR)" 55-70, 1991
11 "CNU-IDEC cell library data book"
12 W.F. McLaughlin, "Asynchronous Protocol Converters for Two-Phase Delay-Insensitive Global Communication" 17 (17): 923-928, 2009
13 오명훈, "Asynchronous 2-Phase Protocol Based on Ternary Encoding for On-Chip Interconnect" 한국전자통신연구원 33 (33): 822-825, 2011
14 E. Nigussie, "Area Efficient Delay-Insensitive and Differential Current Sensing On-chip Interconnect" 143-146, 2008
15 C.T. Hsieh, "Architectural Energy Optimization by Bus Splitting" 21 (21): 408-414, 2002
16 오명훈, "Architectural Design Issues in a Clockless 32 Bit Processor Using an Asynchronous HDL" 한국전자통신연구원 35 (35): 480-490, 2013
17 J. Lee, "A Phase-Based Approach for On-chip Bus Architecture Optimization" 52 (52): 626-645, 2009