부정적 간섭을 제거하는 동적 분기 예상 메커니즘 = A Dynamic Branch Prediction Mechanism to Reduce Negative Interferences

다국어 초록 (Multilingual Abstract)

Superscalar processors require the accurate branch prediction scheme to achieve high performance. Two-level branch predictors have been known to achieve high prediction accuracy. But, when a branch accesses a PHT entry that was previously updated by a different branch, two-level predictors may occur interferences. Negative interferences among interferences have a negative effect on performance, since they can by caused mispredictions.
This paper presents a new dynamic branch predictor which reduces negative interferences. In the proposed predictor, we attach a hit bit to entry in BTB that changes bias bit dynamically in the execution time. In effect, the proposed scheme effectively reduces negative interferences.