낮은 분주비의 위상고정루프에 주파수 체배기와 지연변화-전압 변환기를 사용한 클럭 발생기

참고문헌 (Reference)

1 최영식, "자기잡음제거 전압제어발진기 이용한 위상고정루프" 대한전자공학회 47 (47): 47-52, 2010

2 Floyd M. Gardner, "Charge-Pump Phase-Lock Loop" COM-28 (COM-28): 1849-1858, 1980

3 K. J. Hsiao, "An 8-GHz to 10-GHz distributed DLL for multiphase clock generation" 44 (44): 2478-2487, 2009

4 M. M. Elsayed, "A spur-frequency-boosting PLL with a-74 dBc reference-spur suppression in 90 nm digital CMOS" 48 (48): 2104-2117, 2013

5 S. Hwang, "A self-calibrated DLL-based clock generator for an energy-aware EISC processor" 21 (21): 575-579, 2013

6 C. Kim, "A low-power small-area 7. 28 ps jitter 1 GHz DLL-based clock generator" 37 (37): 1414-1420, 2002

7 J. Choi, "A low power and wide range programmable clock generator with a high multiplication factor" 19 (19): 701-705, 2011

8 K. J. Wang, "A discrete-time model for the design of type-II PLLs with passive sample loop filters" 58 (58): 2011

9 J. H. Nam, "A clock generator with jitter suppressed delay locked loop" 49 (49): 17-22, 2012

10 Kyoohyun Lim, "A Low-Noise Phase-Locked Loop Design by Loop Bandwidth Optimization" 35 (35): 807-815, 2000

11 K. Ryu, "A DLL with dual edge triggered phase detector for fast lock and low jitter clock generator" 59 (59): 1860-1870, 2012

12 G. Chien, "A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications" 35 (35): 1996-1999, 2000