KOA 기반의 유한체 승산기 설계 = Design of Finite Field Multiplier based on KOA

다국어 초록 (Multilingual Abstract)

This paper proposes new multiplicative techniques over finite field, by using KOA. At first, we regenerate the given polynomial into a binomial or a trinomial to apply our polynomial multiplicative techniques. After this, the product polynomial is archived by defined auxiliary polynomials. To perform multiplication over $GF(2^m)$ by product polynomial, a new mod $F({\alpha})$ method is induced. Using the proposed operation techniques, multiplicative circuits over $GF(2^m)$ are constructed. We compare our circuit with the previous one as proposed by Parr. Since Parr's work is premised on $GF((2^4)^n)$, it will not apply to general cases. On the other hand, the our work more expanded adaptive field in case m=3n.

참고문헌 (Reference)

1 H.T. Kung, "Why ssystolic architecture?" 15 : 37-46, jan.1982.

2 E.D. Mastrovito, "VLSI Architectures for Multiplication in Galois Fields Dept. of Electrical Eng." Linkoping Univ. 1991.

3 C.C.Wang, "VLSI Architecture for Computing Multiplications and Inverses in GF" c-34 : 709-717, aug.1985.

4 C.S. Yeh, "Systolic Multipliers for Finite Field GF" c-33 : 357-360,

5 A. Karatsuba, "Multiplication of Multidigit Numbers on Automata" 7 : 595-596, 1963.

6 B. Sunar, "Mastrovito Multiplier for all trinomials" 48 (48): 522-527, May1999.

7 C. Parr, "Efficient Multiplier Architectures for Galois Fields GF" 47 (47): 162-170, feb.1998.

8 J.Omura, "Computational Method and Apparatus for Finite Fields" 4 587 : 627-, 1986.05

9 E.R. Berlekamp, "Bit-Serial Reed-Solomon Encoders" it-28 (it-28): 869-874, nov.1982.

10 이만영, "BCH부호와 Reed-Solomon부호" 1990.

11 C. Parr, "A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Fields" 45 (45): 856-861, 1996.07

12 I.S. Hsu, "A Comparison of VLSI Architecture of Field Multipliers Using Dual" 37 (37): 735-739,

13 B.A. Laws, "A Cellular-Array Multiplier for GF" c-20 : 1573-1578,