컴퓨터 생성 홀로그램의 하드웨어 구현을 위한 버스 구조 분석 = Bus Architecture Analysis for Hardware Implementation of Computer Generated Hologram

다국어 초록 (Multilingual Abstract)

Recently, holography has received much attention as the next generation visual technology. Hologram is obtained by the optical capturing, but in recent years it is mainly produced by the method using computer. This method is named by computer generated hologram (CGH). Since CGH requires huge computational amount, if it is implemented by S/W it can't work in real time. Therefore it should use FPGA or GPU for real time operation. If it is implemented in the type of H/W, it can't obtain the same quality as S/W due to the bit limitation of the internal system. In this paper, we analyze the bit width for minimizing the degradation of the hologram and reducing more hardware resources and propose guidelines for H/W implementation of CGH. To do this, we performs fixed-points simulations according to main internal variables and arithmetics, analyze the numerical and visual results, and present the optimal bit width according to application fields.

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