Sub-surface Damage of Ultra-Thin Monocrystalline Silicon Wafer Induced by Dry Polishing

다국어 초록 (Multilingual Abstract)

Ultra-thin wafer fabrication has become a hot spot in recent years with the growing demand for small size and high performance electronic devices. However, far less research focused on the damage behavior in ultra-thin wafer. In this work, 300 mm diameter silicon wafer was thinned to 6 µm thick by grinding plus ultra-precision dry polishing. The damage behavior before and after the dry polishing was discussed. Mechanical and surface analysis showed that the dry polishing process can help improve the strength and surface uniformity of ultra-thin wafer by removing high pressure phase and micro cracks. Series of nano beam diffraction patterns revealed the stress induced by the thinning process only existed in surface. High resolution transmission electron microscopy images analyzed by geometric phase approach indicated that surface dislocations can move across the wafer and reached bottom device layers during the dry polishing, increasing the risk of electrical deterioration. The findings are of great significance to the study on process optimization of ultra-thin wafer and provide insights into the reliability of advanced electronic packaging.

참고문헌 (Reference)

1 Peña, F, "hyperspy/hyperspy: HyperSpy v1.5"

2 Chen, K. Y., "Ultra-thin electronic device package" 23 (23): 22-26, 2000

3 Gupta, S., "Ultra-thin chips for high-performance flexible electronics" 2 (2): 8-, 2018

4 Kim, Y.S, "Ultra thinning 300-mm wafer down to 7-μm for 3D wafer Integration on 45-nm node CMOS using strained silicon and Cu/Low-k interconnects" 1-4, 2009

5 Liu, X., "Thermomechanical strain measurements by synchrotron X-ray diffraction and data interpretation for through-silicon vias" 103 (103): 022107-, 2013

6 Hirth, J.P, "Theory of Dislocations" Wiley 1982

7 Zhang, Q, "Surface damage mechanism of monocrystalline silicon during single point diamond grinding" 396–397 : 48-55, 2018

8 Zarudi, I., "Subsurface damage in single-crystal silicon due to grinding and polishing" 15 : 586-587, 1996

9 Seibt, M., "Structural and electrical properties of metal impurities at dislocations in silicon" 202 (202): 911-920, 2005

10 Ozdol, V.B, "Strain mapping at nanometer resolution using advanced nano-beam electron diffraction" 106 (106): 253107-, 2015

11 Liu, Y., "Scaling effect of interfacial reaction on intermetallic compound formation in Sn/Cu pillar down to 1 μm diameter" 117 : 146-152, 2016

12 "SEMI: Test method for measurement of chip (Die) strength by mean of 3-point bending"

13 Hÿtch, M. J., "Quantitative measurement of displacement and strain fields from HREM micrographs" 74 (74): 131-146, 1998

14 Baram, M., "Quantitative HRTEM analysis of FIB prepared specimens" 232 (232): 395-405, 2010

15 Hull, R, "Properties of Crystalline Silicon" 1999

16 Zhang, Z., "Phase transformation of single crystal silicon induced by grinding with ultrafine diamond grits" 64 (64): 177-180, 2011

17 Abdelnaby, A, "Numerical simulation of heat generation during the back grinding process of silicon wafers" IEEE 1-4, 2012

18 Johnson, C.L, "Nanoscale waviness of low-angle grain boundaries" 101 (101): 17936-17939, 2004

19 Kang, R., "Microstructure studies of the grinding damage in monocrystalline silicon wafers" 26 (26): 13-18, 2007

20 Chong, D.Y.R, "Mechanical characterization in failure strength of silicon dice" 2 : 2004

21 Yamamoto, K, "Infl uence of threading dislocations on lifetime of gate thermal oxide" Trans Tech Publications 477-480, 2012

22 Inoue, F., "Infl uence of Si wafer thinning processes on(sub)surface defects" 404 : 82-87, 2017

23 Béché, A., "Improved precision in strain measurement using nanobeam electron diff raction" 95 (95): 123114-, 2009

24 Béché, A., "Improved accuracy in nano beam electron diff raction" 209 : 012063-, 2010

25 Lihui Song, "Impact of Various Charge States of Hydrogen on Passivation of Dislocation in Silicon" 대한금속·재료학회 14 (14): 574-580, 2018

26 Tsai, W.L, "How to select adhesive materials for temporary bonding and de-bonding of 200 mm and 300 mm thin-wafer handling for 3D IC integration?" 989-998, 2011

27 Ryhänen, T., "Handbook of Silicon Based MEMS Materials and Technologies" William Andrew Publishing 2010

28 Bertheau, J, "Extreme thinned-wafer bonding using low temperature curable polyimide for advanced wafer level integrations" IEEE 86-91, 2018

29 Min, C., "Experimental study of lattice distortion in ellipsoid-like nano-crystallites of copper" 42 (42): 826-832, 2011

30 Uesugi, F., "Evaluation of two-dimensional strain distribution by STEM/NBD" 111 (111): 995-998, 2011

31 Armigliato, A, "Electron diffraction with ten nanometer beam size for strain analysis of nanodevices" 93 (93): 161906-, 2008

32 Sun, J, "Edge chipping of silicon wafers in rotating grinding" 1099-1103, 2016

33 Che, F. X., "Dynamic stress modeling on wafer thinning process and reliability analysis for TSV wafer" 4 (4): 1432-1440, 2014

34 Kittler, M., "Dislocations as active components in novel silicon devices" 11 (11): 249-258, 2009

35 Siegelin, F, "Dislocation related leakage in advanced CMOS devices" 59-63, 2005

36 Goel, S., "Diamond machining of silicon : a review of advances in molecular dynamics simulation" 88 : 131-164, 2015

37 Maeda, N, "Development of sub 10-μm ultra-thinning technology using device wafers for 3D manufacturing of terabit memory" 105-106, 2010

38 Wang, X.D, "Determination of stacking fault probability in fcc Fe–Mn–Si–Al alloy by electron diffraction" 101 (101): 093511-, 2007

39 Eneman, G., "Defects, junction leakage and electrical performance of Ge pFET devices" 19 (19): 195-205, 2009

40 Leroy, B, "Critical resolved shear stress for a dislocation loop growth, stability and retrogrowth in silicon: application to the 16MEG DRAM" 57–58 (57–58): 275-286, 1997

41 Dash, W., "Copper precipitation on dislocations in silicon" 27 (27): 1193-1195, 1956

42 Cochard, J., "Constitutive modeling of intrinsic silicon monocrystals in easy glide" 107 (107): 033512-, 2010

43 Peters, J. J., "Artefacts in geometric phase analysis of compound materials" 157 : 91-97, 2015

44 Borrero-López, O., "Anisotropy effects on the reliability of single-crystal silicon" 63 (63): 997-1000, 2010

45 Lixiang Zhang, "Analytical prediction for depth of subsurface damage in silicon wafer due to self-rotating grinding process" 한국물리학회 19 (19): 570-581, 2019

46 Lee, S. W., "Analysis of the relation between leakage current and dislocations in GaN-based light-emitting devices" 4 (4): 37-40, 2007

47 Kim, Y. S., "Advanced wafer thinning technology and feasibility test for 3D integration" 107 : 65-71, 2013

48 Aizawa, K., "A Study on Back Grinding Tape for Ultra-thin Chip Fabrication" 1-4, 2018