Self-Power Gating Technique For Low Power Asynchronous Circuit

다국어 초록 (Multilingual Abstract)

In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.

목차 (Table of Contents)

• Abstract
• Ⅰ. Introduction
• Ⅱ. Asynchronous Digital Watch Design
• Ⅲ. Power Gating in Asynchronous Circuit
• Ⅳ. Simulation Results
• Ⅴ. Conclusion
• References

참고문헌 (Reference)

1 "Predictive Technology Model (PTM)"

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4 Akhila Abba, "Improved Power Gating Technique for Leakage Power Reduction" 4 (4): 6-10, 2014

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6 Huan Minh Vo, "Dual-switch power gating revisited for small sleep energy loss and fast wake-up time in sub-45-nm nodes" 8 (8): 232-238, 2011