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      Self-Power Gating Technique For Low Power Asynchronous Circuit

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      https://www.riss.kr/link?id=A105923612

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      다국어 초록 (Multilingual Abstract)

      In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.
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      In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics inste...

      In this paper, Asynchronous Self-Power Gating technique (ASPG) is used to reduce consumption power in asynchronous digital watch application. The power gating control signal is automatically generated by internal system operation characteristics instead of using replica circuit delay or four-phase handshaking protocol. Isolation cell is designed to insert it between power gating domain and normal operation domain. By using self-power gating circuit, asynchronous digital watch application consumes very low power and maintains data during sleep mode. The comparison results show the proposed ASPG technique saves leakage power up to 40.47% and delay time is reduced to 71% compared to the conventional circuit.

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      목차 (Table of Contents)

      • Abstract
      • Ⅰ. Introduction
      • Ⅱ. Asynchronous Digital Watch Design
      • Ⅲ. Power Gating in Asynchronous Circuit
      • Ⅳ. Simulation Results
      • Abstract
      • Ⅰ. Introduction
      • Ⅱ. Asynchronous Digital Watch Design
      • Ⅲ. Power Gating in Asynchronous Circuit
      • Ⅳ. Simulation Results
      • Ⅴ. Conclusion
      • References
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      참고문헌 (Reference)

      1 "Predictive Technology Model (PTM)"

      2 Yvain Thonnart, "Power Reduction of Asynchronous Logic Circuits Using Activity Detection" 17 (17): 893-906, 2009

      3 Chong-Fatt Law, "Modeling and Synthesis of Asynchronous Pipelines" 19 (19): 682-695, 2011

      4 Akhila Abba, "Improved Power Gating Technique for Leakage Power Reduction" 4 (4): 6-10, 2014

      5 Ik Joon Chang, "Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation" 45 (45): 401-410, 2010

      6 Huan Minh Vo, "Dual-switch power gating revisited for small sleep energy loss and fast wake-up time in sub-45-nm nodes" 8 (8): 232-238, 2011

      1 "Predictive Technology Model (PTM)"

      2 Yvain Thonnart, "Power Reduction of Asynchronous Logic Circuits Using Activity Detection" 17 (17): 893-906, 2009

      3 Chong-Fatt Law, "Modeling and Synthesis of Asynchronous Pipelines" 19 (19): 682-695, 2011

      4 Akhila Abba, "Improved Power Gating Technique for Leakage Power Reduction" 4 (4): 6-10, 2014

      5 Ik Joon Chang, "Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation" 45 (45): 401-410, 2010

      6 Huan Minh Vo, "Dual-switch power gating revisited for small sleep energy loss and fast wake-up time in sub-45-nm nodes" 8 (8): 232-238, 2011

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      학술지 이력

      학술지 이력
      연월일 이력구분 이력상세 등재구분
      2024 평가예정 재인증평가 신청대상 (재인증)
      2021-01-01 평가 등재학술지 선정 (계속평가) KCI등재
      2020-12-01 평가 등재후보로 하락 (재인증) KCI등재후보
      2017-01-01 평가 등재학술지 선정 (계속평가) KCI등재
      2016-01-01 평가 등재후보학술지 유지 (계속평가) KCI등재후보
      2015-12-01 평가 등재후보로 하락 (기타) KCI등재후보
      2011-01-01 평가 등재 1차 FAIL (등재유지) KCI등재
      2009-01-01 평가 등재학술지 유지 (등재유지) KCI등재
      2006-01-01 평가 등재학술지 선정 (등재후보2차) KCI등재
      2005-10-17 학술지명변경 외국어명 : 미등록 -> Journal of IKEEE KCI등재후보
      2005-05-30 학술지등록 한글명 : 전기전자학회논문지
      외국어명 : 미등록
      KCI등재후보
      2005-03-25 학회명변경 한글명 : (사) 한국전기전자학회 -> 한국전기전자학회
      영문명 : 미등록 -> Institute of Korean Electrical and Electronics Engineers
      KCI등재후보
      2005-01-01 평가 등재후보 1차 PASS (등재후보1차) KCI등재후보
      2004-01-01 평가 등재후보 1차 FAIL (등재후보1차) KCI등재후보
      2003-01-01 평가 등재후보학술지 선정 (신규평가) KCI등재후보
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      학술지 인용정보

      학술지 인용정보
      기준연도 WOS-KCI 통합IF(2년) KCIF(2년) KCIF(3년)
      2016 0.3 0.3 0.29
      KCIF(4년) KCIF(5년) 중심성지수(3년) 즉시성지수
      0.24 0.22 0.262 0.17
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