계층 버스 NUMA 다중 프로세서 시스템을 위한 효율적인 케쉬 구조 = An Efficient Cache Architecture for NUMA Multiprocessor System Hierarchical Bus

다국어 초록 (Multilingual Abstract)

Since most shared memory multiprocessor machines only support a small number of processors, where there is minimal benefit from the local memory of the NUMA architecture, UMA is most popular for those machines. However, as the number of processor increases, most large-scale shared memory multiprocessor machines utilize a NUMA structure. In this paper, we present a new cluster cache architecture for a NUMA shared memory multiprocessor system with hierarchical bus which can overcome the limitation of scalablilty of single bus shared memory multiprocessor system. The cluster cache architecture enhances the system performance by reducing both the higher level bus contention and memory access latency.