효율적인 SEED 암호알고리즘 구현을 위한 최적화 회로구조 = An Optimum Architecture for Implementing SEED Cipher Algorithm with Efficiency

다국어 초록 (Multilingual Abstract)

This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 128-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array. This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We have designed the circuit with the VHDL coding, implemented with a FPGA of 50,000 gates.

참고문헌 (Reference)

1 송홍복, "SEED형식 암호에서 S박스와 G함수 구성에 관한 연구" 한국통신학회 27 (27): 291-300, 2002

2 정진욱, "SEED와 TDES 암호 알고리즘을 구현하는 암호 프로세서의 VLSI 설계" 동의대학교 166-172, 2000

3 William Stalings, "Network and Internetwork Security" Prentice Hall International Edition 1995

4 Jenes-Peter Kaps, "High Speed FPGA Architecture for the Data Encryption Standard" 1998

5 이선근, "DES의 데이터 처리속도 향상을 위한 변형된 Feistel 구조에 관한 연구" 37 (37): 91-97, 2000

6 Mano, M. Morris, "Computer System Architecture" Prentice Hall(Sd) 260-, 1996

7 H. Feistel, "Block Cipher Cryptographic System" U.S. Patent 1974

8 Young-Ho Seo, "Area Efficient Implementation of 128-bit Block Cipher, SEED" 2000

9 Bruce Schneuer, "Applied Cryptography" Wiley 1996

10 한국정보보호센터, "128비트 블록 암호알고리즘(SEED) 개발 및 분석 보고서" 1998

11 전신우, "128비트 SEED 암호 알고리즘의 고속처리를 위한 하드웨어 구현" 11 (11): 13-23, 2001