범용성과 지능성을 갖는 영상 이미지 병렬 처리기 구조 = Architecture of General and Intelligent Parallel processing system for Image processing

다국어 초록 (Multilingual Abstract)

For real-time image processing and communication, it i necessary to develop a parallel processing system which accesses a lot of image data in parallel. The parallel processing system should have to support a block, a horizontal, a vertical, a forward diagonal and a backward diagonal sub-array of image data because algorithms for image processing are repeatedly processed with those sub-arrays.
Even though both cost and performance of the parallel processing system are improved over van Voorhis and Morrin's memory system, there are several problems. In order to solve the problems, we proposed a general and intelligent parallel processing system. The
A thesis submitted to the Committee of Graduate School, Chungnam National University in partial fulfillment of the requirements for the degree of Master in Electronic Engineering in February 1999.
solution is to process addressing calculating way of vertical sub-array as the same speed as those of the block and horizontal sub-array and reduce the complexity of the address calculation circuits in view point of functional architecture. Also, the other solution is to be provided on general applications by either SIMD or MIMD type in view point for applicable architecture.
The function and performance of the proposed parallel processing system were verified with simulation of CADENCE Verilog-XL which is a simulation package.
The proposed parallel processing system which was developed and verified in this paper can improve speed of image processing, multimedia systems, and so on, because it reduces processing time to image data.
Since high-speed and performance teleconference and VOD have been concerned in these days, marketability of our proposed parallel processing system must be very high.

목차 (Table of Contents)

• 목차
• 제1장 서론 = 1
• 1.1 연구 배경 = 1
• 1.2 연구 목적 = 1
• 1.3 연구 내용 = 2
• 제2장 병렬 처리 장치 및 기억 장치 = 3
• 2.1 관련 연구 및 동향 = 3
• 2.2 병렬 처리 장치 = 4
• 2.2.1 SIMD 처리 장치 = 6
• 2.2.2 MIMD 처리 장치 = 6
• 2.2.3 SIMD와 MIMD 처리 장치 비교 = 7
• 2.3 병렬 기억 장치 = 10
• 2.3.1 Classic SIMD 병렬 기억 장치 = 10
• 2.3.2 Park's SIMD 병렬 기억 장치 = 11
• 2.4 병렬 처리 장치를 이용한 적용 예 = 14
• 2.4.1 얼굴 인식 시스템 = 14
• 2.4.2 인쇄체 인식 시스템 = 17
• 제3장 범용 지능형 병렬 처리기 제안 = 20
• 3.1 제안된 병렬 처리기 제안 = 20
• 3.2 제안된 병렬 처리기의 개선된 특징 = 25
• 3.2.1 응용 구조적 측면 = 25
• 3.2.2 기능 구조적 측면 = 26
• 3.3 병렬 프로그램의 용이성 = 27
• 3.3.1 명령어 세트 = 27
• 제4장 설계 및 구현 = 29
• 4.1 병렬 처리 기의 전체 기능 블록도 = 29
• 4.2 병려 처리 칩의 회로 설계 = 30
• 4.2.1 Control Unit = 30
• 4.2.2 Processing Element Unit = 30
• 4.2.3 Memory Controller Unit = 32
• 4.2.4 Control Memory Unit = 35
• 4.2.5 Memory Module = 36
• 4.3 병렬 처리 칩의 시뮬레이션 = 36
• 4.3.1 SIMD 병렬 처리기 시뮬레이션 = 37
• 4.4 병렬 처리기 적용 예 = 40
• 제5장 결론 = 43
• [참고 문헌] = 45
• 초록 = 46