10 nm 이하 Stacked Nanowire FET의 랜덤 베리에이션 연구 = Study of Process-Induced Random Variation in Sub-10-nm Stacked Nanowire FET

국문 초록 (Abstract)

미래 10nm 이하 CMOS 소자 구조 중 하나로써, gate-all-around nanowire FET (GAA NWFET)가 유망한 후보로 제안되고 있다. GAA NWFET 구조는 기존 planar MOSFET 구조에 비하여 좋은 gate controllability를 가지며, short channel effects를 효과적으로 저하할 수 있다. 게다가 nanowire를 적층한 형태의 stacked nanowire 구조는 여러 개의 channel이 적층되기 때문에 electrostatic integrity를 향상시킬 수 있으며, 높은 layout efficiency를 가진다. 최근 MOSFET 소자 크기의 scaling이 계속되면서, line edge roughness (LER), random dopant fluctuation (RDF), 그리고 work-function variation (WFV)와 같은 현상이 무작위 요소로 고려되고 있다. 이들은 소자의 성능과 안정성에 부정적인 역할로써 작용하며, 공정 과정을 거치면서 불가피하게 소자에 생기는 현상이다. LER은 photolithography 공정 과정에 의해 소자 측벽이 불균일하게 형성되는 것을 일컫는다. 기술이 발전하며, 소자의 물리적 크기가 줄어드는 것만큼 LER의 크기도 줄어들지 못하기 때문에 심각한 부정적 요소로 고려되고 있다. 한편, 최근에 high-k/metal-gate 기술이 적용되면서 gate capacitance를 향상시키고 gate leakage를 줄이는 긍정적인 효과를 얻었다. 하지만 gate의 metal grain granularity 현상으로 소자성능에 무작위 요소로 작용하는 work-function variation (WFV)도 또 다른 하나의 부정적 요소가 되었다. 또한, SiO2 interfacial layer의 defect states로 인하여 발생하는 random interface traps (RIT)도 추가적인 무작위 요소로 고려되고 있다.
이 논문에서는 stacked NWFET에서 LER를 줄일 수 있는 요소를 제안하고 (섹션2), LER와 RIT의 상관관계를 살피며 (섹션3), WFV에 의한 영향을 살펴본다 (섹션 4).

다국어 초록 (Multilingual Abstract)

As one of the promising candidates for sub-10-nm CMOS devices, gate-all-around nanowire FETs (GAA NWFETs) have been proposed. The GAA NWFET structure can achieve a better gate controllability as well as effectively suppress short-channel effects. Moreover, the stacked nanowire structure has improved the electrostatic integrity, because it has multiple stacked channels. The stacked multiple-channel structure can provide great layout efficiency.
As MOSFETs continue to scale, line edge roughness (LER), random dopant fluctuation (RDF), and work-function variation (WFV) have brought forward great concerns regarding their negative effects on the device performance and stability. The LER is a fluctuation of edges along the lines patterned by the photolithography process. The LER has become a larger portion of the physical channel length in MOSFETs because it is not scaled down as much as the physical channel length. Owing to the scaling down of the gate oxide in MOSFETs, high-k/metal-gate (HK/MG) CMOS technology has been introduced. The technology reduces gate leakage and improves the gate capacitance by increasing the physical oxide thickness and reducing the electrical oxide thickness. The metal grain granularity (MGG) of the gate, however, has become one of the variability sources and has induced the work-function variation (WFV).
Further, the HK/MG technology introduced an additional variation source—random interface traps (RIT), although the semiconductor industry has adopted the technology to reduce the gate leakage current as well as to improve the gate controllability. The RIT indicates the defect states in the SiO2 interfacial layer between high-k material and silicon.
This dissertation will suggest the variation-immunity on LER in the stacked nanowire FET (Section 2), the impacts of LER and RIT in stacked nanowire FET (Section3) , and the WFV-induced variation in stacked nanowire FET (Section 4).

목차 (Table of Contents)

• 1. Introduction p.1
• 1.1 Beyond the Planar MOSFET p.1
• 1.2 Process-Induced Random Variation p.3
• 1.3 References p.7
• 2. Study of Line Edge Roughness in Sub-10-nm Stacked Nanowire FETs p.10
• 2.1 Introduction p.10
• 2.2 Line Edge Roughness Model p.12
• 2.3 LER Correlation between Nanowire p.16
• 2.4 Impact of Correlation in-between Nanowires p.18
• 2.5 Impact of Area Difference in-between Nanowire p.22
• 2.6 Impact of the Number of Nanowires p.25
• 2.7 Summary p.28
• 2.8 References p.29
• 3. Impact of Interface Traps and Surface Roughness on the Device Performance of Stacked Nanowire FETs p.33
• 3.1 Introduction p.33
• 3.2 Generating NWSR profiles and Interface Traps p.35
• 3.3 Impact of Interface Traps and NWSR p.40
• 3.4 Correlation of NWSR and Interface Traps p.42
• 3.5 Summary p.48
• 3.6 References p.49
• 4. Study of Work-Function Variation in Stacked Nanowire Structure p.52
• 4.1 Introduction p.52
• 4.2 Stacked Nanowire FET Design and Simulation for WFV p.53
• 4.3 Results and Discussion p.55
• 4.4 Summary p.59
• 4.5 References p.60
• 5. Conclusion p.62
• 국문초록 p.63
• Acknowledgement p.65