Within-Person and between-Person Variability in Learning and Memory

Hsu, Ching-Hsiu ProQuest Dissertations & Theses Stanford Universit 2022 해외박사(DDOD)

Memory performance can vary at two distinct levels: within-person and between-person. Within-person variability reflects the fluctuations in performance over time in a single person; between-person variability reflects the differences in long-term averages that differentiates individuals in a group. Fundamental questions about how and why episodic memory –– that is, memory for events –– varies at the within-person and between-person levels still remain unanswered due to methodological shortcomings. In this thesis, I first illustrate these shortcomings using theoretical and simulation approaches. Then, I report data from repeated-measures studies that sought to understand the variability in episodic memory outcomes at both withinperson and between-person levels by examining how it is related to working memory and sustained attention, cognitive functions that are thought to play important roles in episodic memory processes.In the first study, I conducted a repeated-measures experiment to answer fundamental questions about how memory performance varies. In particular, I examined whether and how between-person (BP) and within-person (WP) variability in episodic memory relates to measures of working memory and sustained attention. First, I found that the majority of the variability in my measures of episodic memory (as well as working memory and sustained attention) can be attributed to the BP level. Second, I found that when episodic memory was measured as immediate recall, both working memory and sustained attention were related to episodic memory at the BP level, while only sustained attention but not working memory was related to episodic memory at the WP level. Third, when episodic memory was measured as delayed recall and these relationships were examined separately at encoding and retrieval, I found largely consistent results to those observed for immediate recall for both working memory and sustained attention, but with reduced effect sizes for the delayed recall results. Moreover, both WP encoding and retrieval findings for delayed recall were consistent with each other and also in agreement with WP findings from immediate recall.In a second study, I sought to understand variability in the effectiveness of a retrievalbased learning intervention aimed at improving memory performance. In particular, I used repeated-measures data to answer fundamental questions about the nature of the testing effect –– that is, the differential improvement in learning from retrieval practice compared to restudy –– and its variability. First, I found that the testing effect varies at both the WP and BP levels, and that most of the variability is at the WP level. Second, almost all individuals show a positive mean testing effect across sessions, suggesting that retrieval practice is a beneficial learning strategy for most individuals. However, when considering fluctuations in the testing effect within individuals, the benefit of retrieval practice is not as stable and there are often sessions where retrieval practice is not beneficial for an individual (or is markedly less beneficial in some sessions relative to others). Third, I did not find compelling evidence that variability in the testing effect is related to variability in the other cognitive functions explored in this experiment: working memory and sustained attention. Together, these results provide valuable insights about the applicability of the testing effect and how the testing effect varies at WP and BP levels.Together, the results from this thesis improve our understanding of learning and memory processes. Methodologically, these studies are novel demonstrations in these areas of research showing that using repeated-measures approaches can uncover valuable information about the variability in episodic memory and the testing effect. From both basic and applied science perspectives, being able to separate WP and BP contributions in the variance-covariance structures of episodic memory and the testing effect led to novel answers to questions that were previously unresolved due to the predominant use of cross-sectional designs. Just as there has been a long history of cross-sectional individual differences studies in learning and memory, I hope that these studies will inspire future studies that use even more optimized and comprehensive repeated-measures designs. More broadly, it will be important to explore the generalizability of these results across multiple dimensions. Are these findings robust to changes in particular elements of the study design such as the stimuli used? How might the variancecovariance structure of cognitive functions change in different experimental conditions such as in-lab vs online? Answering these types of questions will lead to a more complete understanding of both basic and applied aspects of learning and memory.

Profile-guided orchestration of computations for CPU and PIM cores

성현모 Graduate School, Yonsei University 2023 국내석사

Processing-in-memory는3D스택메모리를연산장치와결합하는기술이다. 이는메 모리에 가까운 곳에서 연산을 행함으로써 메인 메모리에서 CPU로의 메모리 이동을 줄임으로써 성능과 에너지 효율성을 모두 챙기려는 기술이다. Processing-in-memory 는임베디드멀티코어아키택쳐와는다른특이한설계를가지고있고이는 Processingin-memory을프로그래밍함에어려움을야기한다. 현재의툴체인은프로그래머들에 게 Processing-in-memory을사용하기위해서직접어느부분을 Processing-in-memory 에서 연산할지 명시하도록 되어있다. 이 영역을 직접 설정하는 것은 하드웨어에 따 라 다르며 소프트웨어 개발 사이클에서 매우 큰 시간 소모를 야기한다. 따라서 그런 한계점을 극복하고자, 이 논문은 Profile-guided-optimization (PGO)를 통해 자동으로 어느부분을 Processing-in-memory에서연산할지찾는방법을제안한다. PGO는프로 그램이 실행되는 동안 수집된 통계로 부터 프로그램을 최적화하는 방법이다. PGO의 과정에서 컴파일러는 프로그램을 프로그래머 대신에 분석하게 된다. 이를 위한 가장 중요한 부분은 Processing-in-memory에서 작동할때 가장 좋은 것 같은 부분을 선출 하는일이다. Processing-in-memory은제한적인성능과높은메모리대역폭을가지고 있기때문에, 메모리집약적인코드부분이이에가장적합하다. 이논문은하드웨어에 따라다른퍼포먼스카운터를 PGO와함께활용하여프로그래머가커널에대한간섭 없이 최적화 하는 기술을 개발했다. 결과적으로 PGO를 이용한 PIM 활성화는 최대 1.35배의속도향상의성능을보였다. Processing-in-memory is a technology that uses 3D-stacking to integrate memory and compute units. It aims to improve performance and reduce energy consumption by moving computations as closely as possible to the main memory, thereby eliminating the overhead of data movements from the main memory to the CPU. Processing-in-memory devices constitute idiosyncratic embedded multicore architectures which are difficult to program. Current tool chains require the programmer to provide annotations for offloading code regions onto the processing-in-memory substrate. These annotations are hardware specific and disruptive to the software engineering design cycle. To overcome this limitation, this thesis suggests applying profile-guided optimization techniques to automate the code offloading process. Profile-guided optimization is an optimization technique that can optimize the program from profiler statistics collected from the actual execution. In the process of the profile-guided-optimization, the compiler will analyze the program instead of the programmer. The key problem is the identification of code regions that are susceptible for offloading. Because processing-in-memory devices have limited compute capacity but high memory bandwidth, memory-bound code regions must be identified. This thesis develops techniques for using hardware performance counters in conjunction with profile-guided optimization to offload code without programmer intervention. Profile-guided optimization for processing-in-memory achieved a speedup of up to a factor of 1.35× compared to the CPU-only execution on the MultiPIM simulator.

Studies on astrocytic interaction to memory-encoding neurons in varying memory states

김주영 서울대학교 대학원 2023 국내박사

Memories are stored in subset of memory-encoding neurons, or engrams, that encode, retrieve, and update memory according to experience. Recently, it was shown in behavioral studies that in addition to neurons, astrocyte, the glial cell of the central nervous system, also actively contribute to the encoding of memory. However, it has not been identified how astrocytes interact with memory-encoding neurons to contribute to memory function, due to technical limitations. To examine the question, novel genetically-encoded tool was developed, labeling the interaction between astrocyte and neuron using enhanced GFP reconstitution across synaptic partners (eGRASP). Using the tool, the specific connection of astrocytes to memory-encoding neurons were identified. After the learning, astrocyte connection to memory-encoding neurons were increased. In comparison, after the memory extinction, astrocyte connection to memory-encoding neurons were decreased, showing that the connection is correlated to memory states. These results strongly suggest that astrocytic connection to memory-encoding neurons is regulated according to memory states, providing the novel mechanism for astrocyte control of memory function. 기억은 엔그램(engram) 세포라고 불리는 신경세포의 일부 집단에 의하여 저장된다. 엔그램 세포는 기억을 저장하고, 재생하고, 업데이트하는 데에 관여한다. 최근 연구에서 신경세포 외에도 중추신경계의 교세포 중 하나인 성상교세포도 기억을 저장하는 데 주체적으로 기여한다는 것이 알려졌다. 하지만, 성상교세포가 기억 기능에 기여하기 위해 기억을 저장하는 엔그램 신경세포와 어떻게 상호 작용하는지는 기술적인 한계로 인해 확인되지 않았다. 본 연구는 astrocyte-eGRASP라고 불리는 형광 표지 기법을 새롭게 개발하여 성상교세포와 뉴런 간의 상호 작용을 확인하고자 하였다. 이 도구를 사용하여, 엔그램 신경세포에 대한 성상교세포의 특이적인 연결 패턴을 확인할 수 있었다. 학습 후, 기억을 저장하는 엔그램 신경세포에 대한 성상교세포 연결이 증가했다. 이에 비하여, 기억이 소멸(memory extinction)된 경우, 기억을 저장하는 엔그램 신경세포에 대한 성상교세포의 연결이 감소하였다. 즉, 기억 상태에 따라 성상교세포 연결이 달라짐을 보여주었다. 이러한 결과는 기억을 저장하는 엔그램 신경세포에 대한 성상교세포 연결이 기억 상태에 따라 조절된다는 것을 강하게 시사하며, 성상교세포가 기억을 조절하는 새로운 기작에 대한 가능성을 제시한다.

NLP 워크로드를 위한 CXL 확장 메모리 내 Prefetcher 설계

최민호 서울대학교 대학원 2024 국내석사

본 논문은 Natural Language Processing (NLP) 워크로드에 최 적화된 prefetch algorithm을 탑재하고, NLP 워크로드와 general 워크로드가 동시 구동되는 상황에서도 성능 저하를 최소화하는 NLP-aware prefetcher에 대한 내용을 담고 있다. CXL memory는 다른 memory expansion 방식에 비해 대역폭이 넓고 latency가 작지만, 그럼에도 local DIMM에 비해 높은 latency 때문에 시스템에 slowdown을 야기한다. 따라서 memory-side prefetcher를 도입함으로써 miss request가 CXL memory에서 소요하는 latency를 숨기고 NLP 워크로드에 최적화 된 성능을 발휘할 수 있다. 또한 thread 별로 여러 metric을 측정, 이를 기준으로 prefetch enable flag와 prefetch degree를 결정하는 thread filtering 기법을 통해 prefetch buffer pollution에 의한 성능 하락을 방지할 수 있다. 마지막으로 외부 메모리로부터 host cache 로 직접 access하는 기술인 direct access cache (DCA) 중 Direct Data I/O (DDIO)를 사용하여 추가적인 IPC 향상을 가능케 했다. 여러 시나리오에서의 성능 분석을 진행한 결과, NLP-aware prefetcher는 NLP 워크로드에 대해 약 11%의 성능 향상이 있었으 며, latency의 경우 50%가 감소하였다. 또한 여러 page를 접근하 는 워크로드에 대해 thread filtering 기능이 효과가 있음을 밝혔고, DDIO를 통해서 1%의 추가적인 IPC 향상이 있었음을 알아냈다. 주요어 : Memory expansion, Prefetcher, CXL, Natrual Language Processing 학 번 : 2022-27177 This paper presents an NLP-aware prefetcher optimized for Natural Language Processing (NLP) workloads, which minimizes performance degradation even when NLP workloads and general workloads are running concurrently. CXL memory, while offering greater bandwidth and lower latency compared to other memory expansion methods, still causes system slowdown due to its higher latency compared to local DIMMs. To address this, a memory-side prefetcher is introduced to hide the latency of miss requests in CXL memory, thereby achieving optimized performance for NLP workloads. Additionally, a thread filtering technique is employed, which measures various metrics per thread to determine the prefetch enable flag and prefetch degree, thereby preventing performance degradation due to prefetch buffer pollution. Finally, the use of Direct Data I/O (DDIO), a technology that allows direct access from external memory to the host cache, enables additional IPC improvements. Performance analysis across various scenarios shows that the NLP-aware prefetcher achieves approximately 11% performance improvement for NLP workloads, and latency is reduced by 50%. Furthermore, the thread filtering feature proves effective for workloads accessing multiple pages, and DDIO contributes an additional 1% IPC improvement. keywords : Memory expansion, Prefetcher, CXL, Natrual Language Processing Student Number : 2022-27177

A DESIGN OF SINGLE-ENDED TRANSMITTER WITH SIGNAL INTEGRITY ENHANCEMENT TECHNIQUES FOR MEMORY INTERFACES

윤재광 서울대학교 대학원 2024 국내박사

A DESIGN OF SINGLE-ENDED TRANSMITTER WITH SIGNAL INTEGRITY ENHANCEMENT TECHNIQUES FOR MEMORY INTERFACES JAEKWANG YUN DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING COLLEGE OF ENGINEERING SEOUL NATIONAL UNIVERSITY In this thesis, we present an energy-efficient crosstalk compensation transmission technique for memory chips and a precise time-domain ZQ calibration method. Memory systems, which utilize multiple parallel channels for high performance, often suffer from signal distortion due to crosstalk, leading to performance degradation. Additionally, errors in the ZQ value due to comparator offsets cause signal reflection and lower signal integrity. To address these issues, we propose a single-ended transmitter incorporating an asymmetric crosstalk compensation technique with phase equalization to enhance memory bandwidth energy efficiency. Moreover, we introduce a time-domain ZQ calibration method that employs a ring-oscillator instead of a comparator to achieve accurate ZQ values. The proposed transmitter significantly reduces crosstalk-induced jitter and data- induced jitter through its asymmetric crosstalk compensation and phase equalization techniques. Fabricated using a 65 nm process, this single-ended transmitter demonstrates impressive energy efficiency, achieving 1.32 pJ/bit per pin at 9 Gb/s and 1.28 pJ/bit per pin at 8 Gb/s. Additionally, our time-domain ZQ calibration method ensures high signal integrity at the memory interface by minimizing errors in ZQ calibration. This method uses a ring- oscillator in place of a comparator to mitigate reflection caused by impedance mismatches. The time-domain ZQ calibration implemented in the 65 nm process achieves a maximum error rate of 1.5% and an average error rate of 0.7%. These innovations collectively enhance the performance and reliability of high-speed memory interfaces. Keywords: Memory interface, single-ended transmitter, asymmetric crosstalk compensation, phase equalization, signal integrity, ZQ calibration, time-domain, impedance mismatch. Student Number: 2017-25122. 본 연구에서 메모리 칩을 위한 에너지-효율적인 누화 보상 송신 기법과 시간-영역의 ZQ 교정을 제시한다. 높은 성능을 위해 다중 병렬 채널을 사용하는 메모리 특성상, 누화로 인한 신호의 왜곡이 메모리 인터페이스의 성능저하를 가져온다. 또한 비교기의 오프셋으로 인한 ZQ값의 오류는 반사를 유발하여 신호 무결성을 저하시킨다. 따라서 우리는 에너지 효율적으로 메모리 대역폭을 늘리기 위해 위상균등화기법이 포함된 비대칭 누화 보상 기법이 들어간 단일-종단 송신기를 제안하였고, 비교기 대신 링-발진기를 사용하여 정확한 ZQ값을 얻을 수 있는 시간-영역의 ZQ 교정을 제안한다. 제안된 송신기는 위상균등화기법이 포함된 비대칭 누화 보상 기법을 가지며, 누화-유발 지터와 데이터-유발 지터를 크게 감소시킨다. 65 nm 공정으로 설계된 이 단일-종단 송신기는 9 Gb/s에서 1.32 pJ/bit의 핀당 에너지 효율을 갖고, 8 Gb/s에서 1.28 pJ/bit의 핀당 에너지 효율을 갖는다. 또한, 메모리 인터페이스에서 신호 무결성을 위해 ZQ 교정의 오류를 최소화 할 수 있는 시간-영역의 ZQ 교정을 제안한다. 이 시간-영역 ZQ 교정은 비교기 대신 링-발진기를 사용하여 임피던스 불일치로 인한 반사를 최소 한다. 65 nm로 구현된 이 시간-영역 ZQ 교정은 최대 오차율이 1.5%이며, 평균 오차율이 0.7%를 갖는다.

Workload-Aware Resource Management for Data-Intensive Applications

이정하 이화여자대학교 대학원 2026 국내박사

The growing deployment of data-intensive workloads across mobile devices, servers, and accelerator-based platforms has exposed fundamental limitations in current memory and storage systems. Many modern applications, including but not limited to deep learning, exhibit access patterns that diverge from the strong locality assumptions underlying conventional caching, memory, and heterogeneous-memory management policies. As a result, performance degradation increasingly arises not from hardware capacity alone but from mismatches between workload behavior and the system software that governs data placement and movement. This dissertation investigates these challenges through three complementary studies, each focusing on a different layer of the system stack. The first study examines mobile on-device inference and shows that model-file access patterns place sustained pressure on the storage hierarchy, reducing the effectiveness of conventional file caching. It introduces a buffering mechanism that leverages Non-Volatile Memory (NVRAM) to mitigate cache pollution and improve responsiveness under resource constraints. The second study analyzes the memory-access characteristics of deep learning training workloads, demonstrating how DRAM exhaustion severely degrades performance. It proposes a DRAM–NVRAM coordination technique that better accommodates training-induced memory pressure. The third study evaluates heterogeneous-memory execution under NVIDIA’s Unified Virtual Memory (UVM). It reveals that fixed-granularity prefetching often mismatches accelerator access behavior and presents an adaptive prefetch strategy that reduces warp stalls and bandwidth waste under oversubscription. Across these studies, the dissertation develops system-level techniques that make memory and storage management more adaptable to workload behavior, particularly when resources are limited. The findings highlight the need for behavior-aware system software as modern platforms incorporate increasingly tiered memory and storage systems and execute a growing diversity of data-intensive workloads. 현대의 모바일 디바이스, 서버, 가속기 기반 시스템 전반에서 데이터 집약적 워크로드가 빠르게 확산되면서, 기존 메모리 및 스토리지 관리 기법의 근본적인 한계가 드러나고 있다. 특히 딥러닝을 포함한 다양한 애플리케이션은 기존 시스템 소프트웨어가 가정하는 강한 지역성을 만족하지 않는 접근 패턴을 보이며, 이로 인해 캐싱, 메모리 관리, 이기종 메모리 관리 정책 사이에서 부조화가 발생하고 성능 저하가 야기된다. 이러한 문제는 단순한 하드웨어 용량 부족이 아니라, 워크로드의 특성과 시스템 관리 정책 간의 불일치에서 기인한다. 본 학위논문은 이러한 문제를 세 가지 상이한 시스템 계층에서 분석하고, 자원이 제한된 환경에서도 성능을 유지하기 위한 시스템 수준의 관리 기법을 제안한다. 첫 번째 연구는 모바일 온디바이스 추론 과정에서 나타나는 모델 파일 접근 패턴을 분석하여, 기존 파일 캐시 전략의 비효율성을 규명하고 NVRAM 기반 버퍼링 기법을 통해 스토리지 병목을 완화하는 방법을 제시한다. 두 번째 연구는 딥러닝 학습 과정에서 DRAM 고갈로 인해 발생하는 급격한 성능 저하를 분석하고, DRAM–NVRAM 협력 기법을 통해 학습 시의 메모리 압박을 완화하는 방안을 제안한다. 세 번째 연구는 NVIDIA Unified Virtual Memory(UVM)의 고정된 프리페치 정책이 실제 가속기 접근 패턴과 부합하지 않는 문제를 분석하고, 배치 단위의 접근 특징을 기반으로 프리페치 단위를 동적으로 조정하는 기법을 제안하여 워프 스톨과 대역폭 낭비를 감소시킨다. 세 연구는 공통적으로 워크로드의 특성을 반영해 메모리 및 스토리지 관리를 적응적으로 수행하는 시스템 소프트웨어의 필요성을 강조한다. 본 논문의 연구 결과는 플랫폼이 점차 다계층 메모리·스토리지 구조를 도입하고 다양한 데이터 집약적 워크로드를 실행하게 되는 환경에서, 행동 기반의 시스템 관리 기법이 더욱 중요해질 것임을 보여준다.

Enhancing the memory architecture to tackle reliability challenges posed by emerging memory technologies

Muhammad, Imran Sungkyunkwan university 2020 국내박사

Memory systems are critical to computing performance. Until recent past, memory storage density has steadily increased, thanks to the continued and consistent technology scaling. However, the existing charge-based memory technologies such as Dynamic Random Access Memory (DRAM) and Flash are reaching their limits in scaling. Meanwhile, the emergence of multi-core systems and memory-intensive workloads such as deep neural networks, has exacerbated the conventional requirements of a high-density and high-bandwidth memory. Among the existing technologies, 3-D integration is seen as a viable option for increasing memory capacity and bandwidth. Considering the issues of leakage and dynamic power consumption with the existing technologies, researchers have also explored some emerging, resistive, non-volatile memory technologies such as the Resistive Random Access Memory (RRAM/ReRAM), Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) and Phase Change Memory (PCM). PCM has been seen as one of the most promising technologies given its features of scalability, no standby power, non-volatility and a better process compatibility. The emerging memory technologies, including PCM, suffer from some unique challenges related to performance and reliability, which must be addressed before their widespread adoption. Among these, reliability concerns are particularly critical. Two of the most important reliability concerns in Phase Change Memory (PCM) include resistance drift and write disturbance. This thesis presents a set of architectural techniques to address resistance drift and write disturbance in Phase Change Memory (PCM). Exploiting the data-dependent nature of the resistance drift problem, two novel data encoding techniques have been presented which reduce the frequency of error-prone data patterns, thus considerably enhancing the memory reliability. In a multi-level cell (MLC) PCM, in the presence of an ECC shecme, the proposed techniques can reduce the line error rate by up to $10^7$ times compared to a conventional MLC PCM which uses ECC without additional data encoding. The reduction in error rate reduces the overhead for error correction which improves performance and energy efficiency. To address write disturbance in PCM, a write disturbance aware programming technique has been proposed. Additionally, two data encoding techniques are proposed to minimize write disturbance in PCM. The introduced schemes are useful in addressing write disturbance both within a word-line and across the bit-lines (in adjacent word-lines). One of the proposed encoding techniques eliminates the possibility of write disturbance within a word-line at cost of a tri-level cell programming in PCM. With elimination of write-disturbance, an otherwise verify and correct (VnC) mechanism is not required, resulting in significant improvement in the write performance and energy efficiency of PCM. The evaluation shows that the reduction in programming latency due to elimination of possibly multiple VnC operations far outweighs the increased write time for a tri-level cell PCM programming. The proposed architectural enhancements for improving PCM reliability are simple yet effective and come at minimal cost, thus making them very practical. A thorough evaluation shows significant improvements by the proposed techniques over the existing state-of-the-art methods.

Enhancing Spatial and Temporal Memory Safety Through Compiler-Based Instrumentation

Hongjoo Jin 고려대학교 정보보호대학원 2025 국내박사

차세대 메모리 ReRAM에 적용 가능한 NbOx 박막의 전기적 특성

배지은 건국대학교 대학원 2012 국내석사

정보화가 진행됨에 따라 기존의 Dynamic Random Access Memory(DRAM), flash memory를 대체할 차세대 메모리 소자의 개발이 점점 더 필요하게 되었다. 양자역학적 한계 때문에 나노 크기로 소자를 만들기 위해서는 3차원 구조를 가지는 ReRAM 구조를 제작해야 한다. 이러한 구조의 소자 구현을 위해서는 switch 역할을 해 줄 수 있는 소자에 대한 연구가 필수적이다. 본 연구에서는 Pulsed Laser Deposition(PLD)를 이용하여 증착 시 온도, 산소 분압, target에 주사되는 laser power를 다양하게 변화시키며 NbOx 박막을 증착 하였다. Scanning Electron Microscope(SEM)을 이용하여 박막의 두께를 측정 하고 전기적 측정을 통하여 박막의 전기적인 특성을 확인하였다. 특히 Nb2O5 박막은 증착시 넣어주는 산소 분압과 온도에 따라 그 전기적인 특성이 변하였으며 특정 조건에서 안정적인 threshold switching이 나타났다. 또한 RAMAN을 이용하여 NbOx 박막의 전기적 특성인 memory와 threshold switching의 특성의 차이를 확인하였다. 더 나아가서 전기적 stress를 조절하여 threshold switching의 특성의 박막을 memory switching의 특성으로 바꿀 수 있음을 확인하였다. 이러한 실험은 switching mechanism을 밝히는데 큰 도움이 될 것이다. Both bi-stable memory and mono-stable threshold switching were observed depending on the thickness of niobium oxide films. In addition, the transition between memory and threshold switching can be induced by changing external electrical stress. Raman spectroscopy data show that grown niobium oxide films consist of a metal-rich surface and an oxygen-rich bulk layer, and that the volume ratio of the two layers depends on film thickness. It is suggested that different characteristics of conducting filaments in the two layers result in thickness dependence of switching types and transition between memory and threshold switching.

A study of primate multi-memory retrieval and selection process through gaze patterns

팽소망 서울대학교 대학원 2023 국내석사

Memory retrieval process often involves the process of selection from multiple associated memories. The aim of this study is to investigate the process of multi-memory retrieval and selection in humans and monkeys. For the human experiments, participants were required to retrieve two long-term spatial memories associated with each visual object and select the context-appropriate memory in the selective location retrieval task. In this task, participants often demonstrated gaze patterns related to multi-memory retrieval in which they gazed at both spatial locations associated with the visual object before the context was given, and then switched to gazing at only the appropriate location. Additionally, this study showed that gaze patterns before context presentation were correlated with different levels of memory accuracy. In the experiments with a monkey, I observed similar gaze patterns during a spatial working memory task requiring selection of spatial memories. The monkey primarily alternated his gaze between the two spatial locations before context presentation and selectively gazed at one of them after context presentation. Overall, gaze patterns showed that multiple spatial memories were retrieved when a cue was given, and the appropriate memory was chosen from those memories. This study suggests that gaze patterns can be used to probe the process of multi-memory retrieval and selection and provide a behavioral task scheme and preliminary results for future studies on retrieval selection in primates. 여러 개의 연합된 기억 중, 현재 상황에 적절한 기억을 선택하는 과정은 필수적이다. 본 연구는 사람과 원숭이를 모델로 다중 기억 인출 및 선택 과정을 눈 움직임 패턴을 이용하여 밝히고, 추후 영장류 대상 기억 인출 선택 과정 연구 기반을 마련하고자 한다. 이를 위해 인간 참가자들을 대상으로는 각 물체와 연합된 두 개의 다중적인 위치 기억 중 현재 상황에 적절한 기억을 선택하게 하는 선택적 기억 인출 과제를 진행했다. 이러한 선택적 기억 인출 과제에서 참가자들은 다중 기억 인출과 관련해 두 위치를 모두 보는 눈 움직임을, 그리고 그중에서 적절한 기억의 선택을 보여주는 목표 기억 선택 눈 움직임을 보였다. 또한 특정 상황이 주어지기 전의 눈 움직임 패턴에 따라 참가자들의 명시적인 기억 응답 정확도가 달라지는 결과를 확인하여 눈 움직임 패턴을 어떤 기억이 인출되고 있는지에 대한 지표로 사용할 수 있음을 검증하였다. 또한, 본 연구는 다중 기억 인출 및 선택 과정 관련 원숭이의 선행적인 행동 결과를 제시하고 있다. 원숭이가 사람 실험에 사용된 과제와 유사한 선택적 위치 작업 기억 과제를 진행하는 동안의 눈 움직임은 사람과 유사하게 두 위치를 번갈아 보다가 상황에 적절한 위치를 보는 패턴이 나타났다. 종합적으로, 본 연구는 영장류 눈 움직임 패턴을 통해 자극이 주어지면 여러 기억이 인출되고, 그중 적절한 기억이 선택된다는 것을 보였다. 이를 통해 본 연구는 추후 영장류 대상 기억 선택 과정 연구의 기반을 마련하였다.