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    • Device and Process Design Based on Functional Oxide Thin Films for Advanced Memory Applications

      고상한 경희대학교 대학원 2025 국내석사

      RANK : 234303

      In this work, we present an integrated approach for implementing high-performance and high- reliability memory technology by precisely controlling the material-specific electrical properties of functional oxide thin films and applying them to the structural design of memory devices. In particular, representative oxide materials such as HfO2, Al2O3, and InGaZnO (IGZO) were applied to various roles such as ferroelectric layers, insulating layers, and channel layers, respectively, and the memory performance parameters such as charge storage characteristics, bias stability, and data retention characteristics of the devices were experimentally verified by controlling the process conditions and the stacked structure, and the possibility of applying them to memory devices was verified. First, the crystallization behavior and ferroelectric characteristic changes were analyzed by introducing an Al2O3 capping layer on an undoped HfO2 thin film. The crystal phase transition and polarization switching characteristics according to the temperature conditions of the HfO2 atomic layer deposition (ALD) process were evaluated, and it was confirmed that the polarization characteristics, leakage current, and endurance of the ferroelectric capacitor with the metal- insulator-ferroelectric-metal (MIFM) structure were significantly improved through the stabilization of the ferroelectric phase, which is the orthorhombic phase (o-phase). This suggests an effective methodology that can implement excellent ferroelectric characteristics only through interface control without separate doping. Second, by designing the IGZO thin film as a double-layer (DL) structure and depositing it with different oxygen partial pressures (PO2) during the sputtering process, we attempted to improve the performance in a 2-transistor-0-capacitor (2T0C) DRAM cell. The heterogeneous interface formed between the upper and lower IGZO layers served as an additional conduction path, and the storage efficiency and retention time were increased by advantageously utilizing the parasitic capacitance through geometric optimization of the active area. Through this, we propose a performance improvement method of 2T0C DRAM cells by combining structural design and material control. Finally, we designed a HfO2/Al2O3 nanolaminate gate insulator (GI) structure to secure electrical reliability while utilizing high-K dielectrics in the thin film transistor (TFT) constituting the 2T0C DRAM cell. By periodically laminating HfO2 and Al2O3 through a 150 °C ALD process, we simultaneously achieved crystallization suppression and interface defect reduction, which led to low-voltage operation and improved bias stress stability. When applied to an actual 2T0C DRAM cell, it was successfully verified by showing excellent long-term retention behavior. These results provide guidelines for the design of insulators for low-temperature oxide transistor- based memories.

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