http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
- 中文 을 입력하시려면 zhongwen을 입력하시고 space를누르시면됩니다.
- 北京 을 입력하시려면 beijing을 입력하시고 space를 누르시면 됩니다.
- 검색키워드
- 주제어 : 병렬처리기 (검색결과 14 건)
-
For real-time image processing and communication, it i necessary to develop a parallel processing system which accesses a lot of image data in parallel. The parallel processing system should have to support a block, a horizontal, a vertical, a forward diagonal and a backward diagonal sub-array of image data because algorithms for image processing are repeatedly processed with those sub-arrays. Even though both cost and performance of the parallel processing system are improved over van Voorhis and Morrin's memory system, there are several problems. In order to solve the problems, we proposed a general and intelligent parallel processing system. The A thesis submitted to the Committee of Graduate School, Chungnam National University in partial fulfillment of the requirements for the degree of Master in Electronic Engineering in February 1999. solution is to process addressing calculating way of vertical sub-array as the same speed as those of the block and horizontal sub-array and reduce the complexity of the address calculation circuits in view point of functional architecture. Also, the other solution is to be provided on general applications by either SIMD or MIMD type in view point for applicable architecture. The function and performance of the proposed parallel processing system were verified with simulation of CADENCE Verilog-XL which is a simulation package. The proposed parallel processing system which was developed and verified in this paper can improve speed of image processing, multimedia systems, and so on, because it reduces processing time to image data. Since high-speed and performance teleconference and VOD have been concerned in these days, marketability of our proposed parallel processing system must be very high.
-
Motion estimation is an efficient method to eliminate temporal redundancy of the image sequences. Among many motion estimation algorithms, the block matching algorithm is widely used because of its simplicity and high efficiency. In this paper, a parallel image processing system is proposed for Full search block matching algorithm, which is based on Park's multi-access memory system. The proposed parallel image processing system consists of microprocessor, instruction queue, DMA controller, and sixty four multi-access memory system. The microprocessor controls instruction queue, DMA controller, PE module in multi-access memory system, and establishes the communication among the host computer and the PE module. The instruction queue and the DMA controller store instruction or output instruction. The multi-access memory system consists of four PEs and five memory modules. The function and performance of the proposed system is simulated by CADENCE Berilog-XL, and the experimental result of proposed system is compared to ones of serial-processing system and previous parallel processing system.
-
Watershed algorithm을 위한 병렬 처리기 구조
The watershed transformation is a mid-level operation used in morphological image segmentation. It is well known that watershed transformations are made of very large amount of data and that many operations per pixel must be performed in order to achieve useful result of segmentation. This thesis proposes a parallel image processing system for watershed algorithm, which is based on Park's multi-access memory system. The proposed parallel image processing system use SIMD computer together with MIMD computer architecture for making to parallelize watersheds. The proposed parallel image processing system consists of microprocessor, PE modules, DMA controller and sixty seven multi-access memory systems. The microprocessor controls DMA controller, each PE modules, and establish the communication among the host computer and the PE module. The multi-access memory system consists of four PEs and five memory modules. The function and performance of the proposed architecture is simulated and verified by Cadence Verilog-XL, and we shows that the matrix operation such as comparision with pixels can be effectively implemented with the proposed architecture. Experimental result of proposed system is compared to result of serial-processing systme.
-
Gray-scale morphological 필터를 위한 병렬 처리기
Image processing is used to enhance digital images thus making further analysis easier, faster or more reliable. Morphology image processing is a local technique used to implement many spatial and gray-scale filters, and those algorithms are utilized in many machine vision systems because it is a very powerful image processing tool. Morphology analyses the images from the perspective of set theory and geometry. In the morphological aproach an image is analyzed i terms of some predetermained geometric shape known as structuring element. In this thesis, an efficient parallel image processing system is proposed for gray-scale morphological filtersm, which is based on Park's multiple-access memory system. The proposed parallel image processing system is a fully synchronous SIMD computer with pipelined architecture. It consists, mainly of a microprocessor and two PE modules which has four processing elements and five memory modules each. The microprocessor controls the activities of each PE, and establish the communication among the host and the PEs. The function and performance of the proposed architecture is simulated and verified by CADENCE Verulog-XL, and we shows that the basic morphological operations such as dilation, erosion, and algorithms such as edge detection can be easily and effectively implemented with the proposed architecture. Experimental results indicate that the pipelined PE architecture is very powerful compared to general-purpose computer and previous parallel processor system.
-
-
-
-
-
-
연관 검색어 추천
이 검색어로 많이 본 자료
활용도 높은 자료
