The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application

Lee, Kwyro,Nam, I.,Kwon, Ickjin,Gil, J.,Han, Kwangseok,Park, S.,Seo, Bo-Ik IEEE 2005 IEEE transactions on electron devices Vol.52 No.7

The impact of CMOS technology scaling on the various radio frequency (RF) circuit components such as active, passive and digital circuits is presented. Firstly, the impact of technology scaling on the noise and linearity of the low-noise amplifier (LNA) is thoroughly analyzed. Then two new circuits, i.e., CMOS complementary parallel push-pull (CCPP) circuit and vertical-NPN (V-NPN) circuit for direct-conversion receiver (DCR), are introduced. In CCPP, the high RF performance of pMOS comparable to nMOS provides single ended differential RF signal processing capability without the use of a bulky balun. The use of parasitic V-NPN bipolar transistor, available in triple well CMOS technology, has shown to provide more than an order of magnitude improvement in 1/f noise and dc offset related problems, which have been the bottleneck for CMOS single chip integration. Then CMOS technology scaling for various passive device performances such as the inductor, varactor, MIM capacitor, and switched capacitor, is discussed. Both the forward scaling of the active devices and the inverse scaling of interconnection layer, i.e., more interconnection layers with effectively thicker total dielectric and metal layers, provide very favorable scenario for all passive devices. Finally, the impact of CMOS scaling on the various digital circuits is introduced, taking the digital modem blocks, the various digital calibration circuits, the switching RF power amplifier, and eventually the software defined radio, as examples.

Optimization of Low Power CMOS Baseband Analog Filter-Amplifier Chain for Direct Conversion Receiver

Minkyung Lee,Ickjin Kwon,Kwyro Lee 대한전자공학회 2004 Journal of semiconductor technology and science Vol.4 No.3

A low power CMOS receiver baseband analog circuit based on alternating filter and gain stages reported. For the given specifications of the baseband analog block, optimum allocation of the gain, IIP3 and NF of the each block was performed to minimize current consumption. The fully integrated receiver BBA chain is fabricated in 0.18 I'm CMOS technolog} and IIP3 of 30 dBm with a gain of 55 dB and noise figure of 31 dB are obtained at 4.86 mW power consumption.<br/>

<i>In Vivo</i> Silicon-Based Flexible Radio Frequency Integrated Circuits Monolithically Encapsulated with Biocompatible Liquid Crystal Polymers

Hwang, Geon-Tae,Im, Donggu,Lee, Sung Eun,Lee, Jooseok,Koo, Min,Park, So Young,Kim, Seungjun,Yang, Kyounghoon,Kim, Sung June,Lee, Kwyro,Lee, Keon Jae American Chemical Society 2013 ACS NANO Vol.7 No.5

<P>Biointegrated electronics have been investigated for various healthcare applications which can introduce biomedical systems into the human body. Silicon-based semiconductors perform significant roles of nerve stimulation, signal analysis, and wireless communication in implantable electronics. However, the current large-scale integration (LSI) chips have limitations in <I>in vivo</I> devices due to their rigid and bulky properties. This paper describes <I>in vivo</I> ultrathin silicon-based liquid crystal polymer (LCP) monolithically encapsulated flexible radio frequency integrated circuits (RFICs) for medical wireless communication. The mechanical stability of the LCP encapsulation is supported by finite element analysis simulation. <I>In vivo</I> electrical reliability and bioaffinity of the LCP monoencapsulated RFIC devices are confirmed in rats. <I>In vitro</I> accelerated soak tests are performed with Arrhenius method to estimate the lifetime of LCP monoencapsulated RFICs in a live body. The work could provide an approach to flexible LSI in biointegrated electronics such as an artificial retina and wireless body sensor networks.</P><P><B>Graphic Abstract</B> <IMG SRC='http://pubs.acs.org/appl/literatum/publisher/achs/journals/content/ancac3/2013/ancac3.2013.7.issue-5/nn401246y/production/images/medium/nn-2013-01246y_0006.gif'></P><P><A href='http://pubs.acs.org/doi/suppl/10.1021/nn401246y'>ACS Electronic Supporting Info</A></P>

A Small Sized Differential Inverted-F Antenna With Balun For WPAN

Myeungsu Kim,Kwyro Lee 한국통신학회 2005 한국통신학회 학술대회논문집 Vol.2005 No.6

3- Transistor Cell OTP ROM Array Using Standard CMOS Gate-Oxide Antifuse

Jinbong Kim,Kwyro Lee 대한전자공학회 2003 Journal of semiconductor technology and science Vol.3 No.4

An integrated low power highly linear 2.4-GHz CMOS receiver front-end based on current amplification and mixing

Kwon, Ickjin,Lee, Kwyro IEEE 2005 IEEE microwave and wireless components letters Vol.15 No.1

A low power 2.4-GHz complementary metal oxide semiconductor (CMOS) receiver front-end using highly linear mixer based on current amplification and mixing is reported. In the proposed mixer, linearity is greatly improved by using current mirror amplifier and transconductance linearization using multiple gated transistors. Single IF direct conversion receiver (DCR) architecture is used to achieve higher level of integration and to relax the problem of DCR. The fully integrated receiver front end is fabricated in 0.18-μm CMOS technology and HP3 of -9 dBm with a gain of 32 dB and noise figure of 6.5 dB are obtained at 8.8 mW power consumption.

A 23.4 mW 68 dB Dynamic Range Low Band CMOS Hybrid Tracking Filter for ATSC Digital TV Tuner Adopting RC and Gm-C Topology

Kuduck Kwon,Kwyro Lee IEEE 2011 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 1 R Vol.58 No.10

<P>In this paper, a 48-200 MHz CMOS hybrid tracking low-pass filter with low power and high dynamic range is presented to solve a local oscillator harmonic-mixing problem for Advanced Television Systems Committee terrestrial digital TV tuner integrated circuits. For low power consumption, the first-order passive RC filter and the second-order transconductor-C filter are combined to implement the third-order Chebyshev tracking low-pass filter. A transconductor linearization technique based on a method of multiple gated transistors is adopted to achieve high dynamic range. Fabricated in a 0.18 μm CMOS process, it achieves a maximum in-band input-referred noise density of 5.1 nV/√Hz and maximum in-band output-referred third-order intercept point of 17.3 dBm, while dissipating 23.4 mW with 1.8 V. The total chip area is 0.6 mm × 0.4 mm.</P>

Highly Linear Silicon-on-Insulator CMOS Digitally Programmable Capacitor Array for Tunable Antenna Matching Circuits

Donggu Im,Kwyro Lee IEEE 2013 IEEE microwave and wireless components letters Vol.23 No.12

<P>A stacked-FET linear 4-bit silicon-on-insulator (SOI) CMOS switched capacitor array is designed for use in tunable antenna matching circuits. A New biasing strategy without negative bias voltage is proposed to circumvent drawbacks such as digital switching noise and harmonics feed-through to the antenna. The proposed switched capacitor array shows almost identical power handling capability to that of the conventional version with negative bias voltage. Compared to other works in SOI or silicon-on-sapphire (SOS) technologies, it shows a comparable or better quality factor, tuning range, power handling capability, and harmonic distortion while consuming ultra low power.</P>

Iterative Demodulation, Decoding and Estimation for LDPC-Coded MIMO-OFDM Systems

Sungchung Park,Kwyro Lee,Sin-Chong Park 대한전자공학회 2005 ITC-CSCC :International Technical Conference on Ci Vol.2005 No.3

A Self-Tuned Balun-LNA With Differential Imbalance Correction and Blocker Filtering

Jaeyoung Choi,Donggu Im,Kwyro Lee IEEE 2011 IEEE microwave and wireless components letters Vol.21 No.12

<P>A CMOS self-tuned low noise amplifier (LNA) with single-to-differential function is presented. A tuned LNA with high-Q band-pass filtering is reconfigured to an oscillator simply by enabling a positive feedback buffer. Using the proposed LNA, an RF filter can be self-tuned without additional tone-generator circuits, and the calibration system is greatly simplified. By adopting a differential hybrid voltage buffer, differential imbalance is minimized. For a proof-of-concept, the proposed LNA is implemented using a 0.18 μm CMOS process. The circuit operates in a tuning range of 0.8-1.5 GHz, while the error between oscillation and center frequency is less than 5%. A pass band gain of 26.7-30 dB, a noise figure (NF) of 3.9-4.3 dB, and an in/out band IIP3 of -9.9/+10.6 dBm are obtained. The LNA consumes 9 mA with 1.8 V supply.</P>