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RF Characteristics of 0.18- m CMOS Transistors
Kwangseok HAN 한국물리학회 2002 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.40 No.1
In this work, the high-frequency performance of a 0.18-m CMOS device has been analyzed with various multi-nger layouts and biases to nd the optimal condition. The optimal bias condition to maximize the cutoff frequency (fT ) and the maximum oscillation frequency (fmax) have been found to be equal to that required to maximize the transconductance (gm). At this bias condition, fT tends to be maximized with a small number of fingers. It has been found that fmax strongly depends on the gate resistance. Finally, the de-embedding effects on cuto frequency are presented.
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Kwangseok Han,Hyungcheol Shin,Kwyro Lee 한국물리학회 2004 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.44 No.1
In this work, a physics-based drain current thermal noise model for short-channel MOSFETs was derived. The proposed model takes into account the velocity-saturation effect explicitly and the carrier heating effect implicitly in the gradual channel region. A diffusion noise source was used to model the local noise generated in a segment of the inversion layer macroscopically, and the impedance field was recalculated when considering the velocity saturation effect. Finally, the proposed model suggests that the increase in the thermal noise for short-channel MOSFETs originates dominantly from the channel length modulation effect.
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Han, Kwangseok,Gil, J.,Song, Seong-Sik,Han, Jeonghu,Shin, Hyungcheol,Kim, Choong-Ki,Lee, Kwyro IEEE 2005 IEEE journal of solid-state circuits Vol.40 No.3
Taking a velocity saturation effect and a carrier heating effect in the gradual channel region, complete thermal noise modeling of short-channel MOSFETs including the induced gate noise and its correlation coefficients is presented and verified extensively with experimentally measured data. All of the four noise models have excellently predicted experimental data with maximal error less than 10% for the deep-submicron MOSFETs. Using these models and a simultaneous matching technique for both optimal noise and power, a low noise CMOS amplifier optimized for 5.2-GHz operation has been designed and fabricated. Experiments using an external tuner show that both NF<SUB>50</SUB> and NF<SUB>min</SUB> are very close to 1.1 dB, which is an excellent figure of merit among reported LNAs.
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