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Nikhil Tiwale,Satyaprasad P. Senanayak,Juan Rubio-Lara,Yury Alaverdyan,Mark E. Welland 대한금속·재료학회 2019 ELECTRONIC MATERIALS LETTERS Vol.15 No.6
Solution processing of metal oxide-based semiconductors is an attractive route for low-cost fabrication of thin flms devices. ZnO thin flms were synthesized from one-step spin coating-pyrolysis technique using zinc neodecanoate precursor. X-raydifraction (XRD), UV–visible optical transmission spectrometry and photoluminescence spectroscopy suggested conversionto polycrystalline ZnO phase for decomposition temperatures higher than 400 °C. A 15 % precursor concentration was foundto produce optimal TFT performance on annealing at 500 °C, due to generation of sufcient charge percolation pathways. Thedevice performance was found to improve upon increasing the annealing temperature and the optimal saturation mobility of0.1 cm2V−1 s−1 with ION/IOFF ratio~107was achieved at 700 °C annealing temperature. The analysis of experimental resultsbased on theoretical models to understand charge transport envisaged that the grain boundary depletion region is major sourceof deep level traps and their efective removal at increased annealing temperature leads to evolution of transistor performance.
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Low Power Correlator Using Signal Range and Sub Word Based Clock Gating Scheme
A. Ranganayakulu,K. Satyaprasad 보안공학연구지원센터 2016 International Journal of Hybrid Information Techno Vol.9 No.3
VLSI designers are being motivated to explore the opportunities in low power design at different levels of abstraction in the fast growing mobile and battery power devices market. Research of the past few decades has been resulted in efficient electronic design automation tools which can be applied at several circuit and device level techniques to reduce power consumption. Research is being conducted to explore new techniques to utilize the application of specific signaling characteristics to reduce the power consumption. Few types of clock gating based power reduction techniques are established in present day EDA tools. The proposed research work presents novel sub word partitioned signal range based clock gating technique, which can be very efficient in signal processing applications. A scalable VHDL model is developed for the Correlator architecture with the proposed clock gating scheme. MATLAB script generated test data is used for functional verification. Xilinx FPGA based synthesis and power analysis tools are employed to analyze the power optimization of proposed architecture. The simulation results demonstrate power optimization without compromising on the performance. The results show power saving up to 31% for narrow band signal input conditions.
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