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1
Mobile taxi booking application service’s continuance usage intention by users

Weng, Gooi Sai,Zailani, Suhaiza,Iranmanesh, Mohammad,Hyun, Sunghyup Sean Pergamon 2017 Transportation Research Part D. Transport & Enviro Vol.57 No.-
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Abstract The long-term development of a mobile booking taxi application service depends on the continued use of its passengers. The aim of this study is to investigate the determinants of the mobile taxi booking application service’s continuance intention, using the technology continuance theory by including the perceived risk and subjective norms. The data were collected by surveying 387 users of the mobile taxi application service. The data were analysed by applying the partial least squares technique. The analysis showed that the technology continuance theory has extensive power to explain the continuance intention to use the mobile booking taxi application. Subjective norms also have a significant effect on the attitude of mobile booking taxi application users which represents an important contribution to technology continuance theory extension. The theoretical and practical significances of the study have been discussed. Highlights <UL> <LI> The early acceptance of an MTB Apps does not guarantee continuation. </LI> <LI> Studies on continuance intention of users toward MTB App use are still lacking. </LI> <LI> Results will help App developers to grasp the factors that result in continued MTB App use. </LI> </UL>
2
A 4x Time-Domain Interpolation 6-bit 3.4 GS/s 12.6 ㎽ Flash ADC in 65 ㎚ CMOS

Jianwei Liu,Chi-Hang Chan,Sai-Weng Sin,Seng-Pan U,Rui Paulo Martins 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.4
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- 복사/대출신청
A 6-bit 3.4 GS/s flash ADC in a 65 ㎚ CMOS process is reported along with the proposed 4x time-domain interpolation technique which allows the reduction of the number of comparators from the conventional 2N-1 to 2N-2 in a N-bit flash ADC. The proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage where only offset between the 2N-2 comparators needs to be calibrated. The offset in SR-latches is within ±0.5 LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The design considerations of the proposed technique are detailed in this paper. The prototype achieves 3.4 GS/s with 5.4-bit ENOB at Nyquist and consumes 12.6 ㎽ power at 1 V supply, yielding a Walden FoM of 89 fJ/conversion-step.
3
A 4x Time-Domain Interpolation 6-bit 3.4 GS/s 12.6 mW Flash ADC in 65 nm CMOS

Liu, Jianwei,Chan, Chi-Hang,Sin, Sai-Weng,U, Seng-Pan,Martins, Rui Paulo The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.4
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A 6-bit 3.4 GS/s flash ADC in a 65 nm CMOS process is reported along with the proposed 4x time-domain interpolation technique which allows the reduction of the number of comparators from the conventional $2^N-1$ to $2^{N-2}$ in a N-bit flash ADC. The proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage where only offset between the $2^{N-2}$ comparators needs to be calibrated. The offset in SR-latches is within ${\pm}0.5$ LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The design considerations of the proposed technique are detailed in this paper. The prototype achieves 3.4 GS/s with 5.4-bit ENOB at Nyquist and consumes 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/conversion-step.