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Jae Hoon Lee,Jae-Chern Yoo,Tae Hee Han IEEE 2014 Journal of Lightwave Technology Vol.32 No.18
<P>An optical network-on-chip (NoC) has attracted increasing attention with the advancement of silicon photonics technology due to the explosive growth in communication traffic in system-on-chip and the diminishing returns of miniaturized metal interconnect. Compared with the traditional metallic interconnect, the optical interconnect has superior effective bandwidth, transmission latency, and power consumption. In this paper, we establish an algorithmic optical router design framework to minimize the insertion loss, which is the loss of signal power resulting from the insertion of microring resonators and waveguide crossings. By incorporating system-level considerations on the topology, routing algorithm, and traffic pattern in the optical NoC, the proposed technique provides a rapid design environment for a wide range of application-specific optical NoC architectures with minimized optical signal power loss.</P>
증례보고 : 기도 협착 환자에서 체외순환 보조를 이용한 마취 경험 -증례보고-
이재명 ( Jae Myeong Lee ),임경실 ( Kyung Sil Im ),노희천 ( Hee Chern No ),정현주 ( Hyun Ju Jung ) 대한마취과학회 2007 Korean Journal of Anesthesiology Vol.52 No.6
In tracheal stenosis, airway management is most challenging for anesthesiologists. A small sized endotracheal tube, laryngeal mask airway, with high frequency jet ventilation can be used, but may result in ineffective oxygenation and ventilation. In such cases, extracorporeal life support, ECLS, can be helpful. Herein, a case of tracheal stenosis in an adult assisted with the ECLS is reported. (Korean J Anesthesiol 2007; 52: 719~23)
Chang-Lin Li,Jae-Chern Yoo,Tae Hee Han 대한전자공학회 2018 Journal of semiconductor technology and science Vol.18 No.3
The voltage-frequency island (VFI) design paradigm has strong potential for reducing energy consumption in network-on-chip (NoC). The V/F of each island can be dynamically tuned according to the application’s requirements. However, dynamic VFI (DVFI) requires an efficient on-chip communication architecture to compensate for the latency overhead produced while tuning the proper V/F of each VFI. Although standard topology has been used in most VFI designs, this approach incurs a large energy and latency overhead owing to the redundant hop counts. Therefore, we propose a custom topology-based DVFI for an energy-efficient manycore platform to maximize energy efficiency with a reasonable implementation cost. In this regard, a custom topology generation method with a heuristic run-time V/F tuning algorithm is incorporated by considering the core and link utilization. Experimental results demonstrated the effectiveness of the proposed scheme in terms of execution time and energy-delay product.
Li, Chang-Lin,Yoo, Jae-Chern,Han, Tae Hee The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.6
The voltage-frequency island (VFI) design paradigm has strong potential for achieving high energy efficiency in communication centric manycore system-on-chip (SoC) design called network-on-chip (NoC). However, because of the diminished scaling of wire-dimension and supply voltage as well as threshold voltage in modern CMOS technology, the vulnerability to link failure in VFI NoC is becoming a crucial challenge. In this paper, we propose an energy-optimized topology generation technique for VFI NoC to cope with permanent link failures. Based on the energy consumption model, we exploit the on-chip communication traffic patterns and characteristics of link failures in the early design stage to accommodate diverse applications and architectures. Experimental results using a number of multimedia application benchmarks show the effectiveness of the proposed three-step custom topology generation method in terms of energy consumption and latency without any degradation in the fault coverage metric.
Chang-Lin Li,Jae-Chern Yoo,Tae Hee Han 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.6
The voltage-frequency island (VFI) design paradigm has strong potential for achieving high energy efficiency in communication centric manycore system-on-chip (SoC) design called network-on-chip (NoC). However, because of the diminished scaling of wire-dimension and supply voltage as well as threshold voltage in modern CMOS technology, the vulnerability to link failure in VFI NoC is becoming a crucial challenge. In this paper, we propose an energy-optimized topology generation technique for VFI NoC to cope with permanent link failures. Based on the energy consumption model, we exploit the on-chip communication traffic patterns and characteristics of link failures in the early design stage to accommodate diverse applications and architectures. Experimental results using a number of multimedia application benchmarks show the effectiveness of the proposed three-step custom topology generation method in terms of energy consumption and latency without any degradation in the fault coverage metric.
Choi, Min-Seong,Yoo, Jae-Chern Humana Press 2015 Applied biochemistry and biotechnology Vol.175 No.8
<P>We report a fully automated DNA purification platform with a micropored membrane in the channel utilizing centrifugal microfluidics on a lab-on-a-disc (LOD). The microfluidic flow in the LOD, into which the reagents are injected for DNA purification, is controlled by a single motor and laser burst valve. The sample and reagents pass successively through the micropored membrane in the channel when each laser burst valve is opened. The Coriolis effect is used by rotating the LOD bi-directionally to increase the purity of the DNA, thereby preventing the mixing of the waste and elution solutions. The total process from the lysed sample injection into the LOD to obtaining the purified DNA was finished within 7 min with only one manual step. The experimental result for Salmonella shows that the proposed microfluidic platform is comparable to the existing devices in terms of the purity and yield of DNA.</P>
Li, Chang-Lin,Yoo, Jae-Chern,Han, Tae Hee The Institute of Electronics and Information Engin 2018 Journal of semiconductor technology and science Vol.18 No.3
The voltage-frequency island (VFI) design paradigm has strong potential for reducing energy consumption in network-on-chip (NoC). The V/F of each island can be dynamically tuned according to the application's requirements. However, dynamic VFI (DVFI) requires an efficient on-chip communication architecture to compensate for the latency overhead produced while tuning the proper V/F of each VFI. Although standard topology has been used in most VFI designs, this approach incurs a large energy and latency overhead owing to the redundant hop counts. Therefore, we propose a custom topology-based DVFI for an energy-efficient manycore platform to maximize energy efficiency with a reasonable implementation cost. In this regard, a custom topology generation method with a heuristic run-time V/F tuning algorithm is incorporated by considering the core and link utilization. Experimental results demonstrated the effectiveness of the proposed scheme in terms of execution time and energy-delay product.
딥러닝을 통한 페트병 자동 분리수거 재활용률 개선 시스템
박준석 ( Jun-seok Park ),유재천 ( Jae-chern Yoo ) 한국정보처리학회 2022 한국정보처리학회 학술대회논문집 Vol.29 No.2
최근 소비경제의 폭발적 성장과 더불어 쓰레기로 인해 우리 생활 주변은 물론 해양까지 환경오염이 점점 심각해지고 있다. 그에 따른 재활용 시스템의 필요성이 높아지고 있으며, 지속 가능한 발전을 위해 세계적으로 환경을 위한 연구가 진행되고 있다. 본 논문에서는 딥러닝 기반의 AI 기술을 적극적으로 활용하여 분리수거가 아닌, 페트병을 재활용하는 과정을 집중적으로 개선한다. 이를 통하여, 페트병이 원인인 환경오염을 해결할 뿐만 아니라 고급 재활용 원료를 생산할 수 있게 하여 경제적인 효과도 얻을 수 있는 시스템을 제안한다.