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        • A Low Power Broadband Differential Low Noise Amplifier Employing Noise and IM3 Distortion Cancellation for Mobile Broadcast Receivers

          Donggu Im,Ilku Nam,Kwyro Lee IEEE 2010 IEEE microwave and wireless components letters Vol.20 No.10

          <P>A CMOS broadband differential low noise amplifier (LNA) employing noise and third order intermodulation (IM3) distortion cancellation has been designed using a 0.13 μm CMOS process for mobile TV tuners. By combining a common gate amplifier with a common source amplifier through a current mirror, a high gain due to the additional current amplification and a low noise figure (NF) due to the thermal noise cancellation can be achieved with low power consumption without degrading the input matching. To improve the linearity with low power consumption, a multiple gated transistor technique for canceling the IM3 distortion is adopted. The proposed LNA has a maximum gain of 14.5 dB, an averaged NF of 3.6 dB, an IIP3 of 3 dBm, an IIP2 of 38 dBm, and an |Sn<SUB>11</SUB>| lower than -9 dB in a frequency range from 72 to 850 MHz. The power consumption is 9.6 mW at a 1.2 V supply voltage and the chip area is 0.08 mm<SUP>2</SUP>.</P>

        • A Wideband CMOS Low Noise Amplifier Employing Noise and IM2 Distortion Cancellation for a Digital TV Tuner

          Im, Donggu,Nam, Ilku,Kim, Hong-Teuk,Lee, Kwyro IEEE 2009 IEEE journal of solid-state circuits Vol.44 No.3

          <P> A wideband CMOS low noise amplifier (LNA) with single-ended input and output employing noise and IM2 distortion cancellation for a digital terrestrial and cable TV tuner is presented. By adopting a noise canceling structure combining a common source amplifier and a common gate amplifier by current amplification, the LNA obtains a low noise figure and high IIP3. IIP2 as well as IIP3 of the LNA is important in broadband systems, especially digital terrestrial and cable TV applications. Accordingly, in order to overcome the poor IIP2 performance of conventional LNAs with single-ended input and output and avoid the use of external and bulky passive transformers along with high sensitivity, an IM2 distortion cancellation technique exploiting the complementary RF performance of NMOS and PMOS while retaining thermal noise canceling is adopted in the LNA. The proposed LNA is implemented in a 0.18 <TEX>$\mu\hbox{m}$</TEX> CMOS process and achieves a power gain of 14 dB, an average noise figure of 3 dB, an IIP3 of 3 dBm, an IIP2 of 44 dBm at maximum gain, and S11 of under <TEX>${- 9}~{\rm dB}$</TEX> in a frequency range from 50 MHz to 880 MHz. The power consumption is 34.8 mW at 2.2 V and the chip area is 0.16 <TEX>${\rm mm}^{2}$</TEX>. </P>

        • A CMOS Active Feedback Balun-LNA With High IIP2 for Wideband Digital TV Receivers

          Donggu Im,Ilku Nam,Kwyro Lee IEEE 2010 IEEE transactions on microwave theory and techniqu Vol.58 No.12

          <P>A wideband active feedback single-to-differential (S-to-D) low-noise amplifier (LNA) for digital TV (DTV) tuners composed of a S-to-D converter, a voltage combiner, and a negative feedback network is proposed to achieve low noise as well as to improve the linearity performances (IIP2 and IIP3) simultaneously. By feeding the single-ended output of the voltage combiner, which is used for combining the differential output of the S-to-D converter, to the input of the LNA through the feedback network, a wideband S-to-D LNA exploiting negative feedback is implemented. The differential mode operation of the voltage combiner reduces the second-order nonlinearity feedback, allowing us to improve both the IIP3 and IIP2 of the LNA at the same time. Two LNA design examples are presented to demonstrate usefulness of the proposed approach. The LNA I, by adopting a common source (CS) amplifier with a common gate, common source (CGCS) balun load as the S-to-D converter, is able to achieve a high gain and a low noise figure (NF) by increasing the loop gain. The LNA II using the differential amplifier with the ac-grounded second input terminal is designed for robust IIP2 to PVT variations.</P>

        • SCISCIESCOPUS

          A Stacked-FET Linear SOI CMOS Cellular Antenna Switch With an Extremely Low-Power Biasing Strategy

          Donggu Im,Bum-Kyum Kim,Do-Kyung Im,Kwyro Lee Professional Technical Group on Microwace Theory a 2015 IEEE transactions on microwave theory and techniqu Vol.63 No.6

          <P>A stacked field-effect transistor (FET) linear cellular antenna switch adopting a transistor layout with odd-symmetrical drain-source metal wiring and an extremely low-power biasing strategy has been implemented in silicon-on-insulator CMOS technology. A multi-fingered switch-FET device with odd-symmetrical drain-source metal wiring is adopted herein to improve the insertion loss (IL) and isolation of the antenna switch by minimizing the product of the on-resistance and off-capacitance. To remove the spurious emission and digital switching noise problems from the antenna switch driver circuits, an extremely low-power biasing scheme driven by only positive bias voltage has been devised. The proposed antenna switch that employs the new biasing scheme shows almost the same power-handling capability and harmonic distortion as a conventional version based on a negative biasing scheme, while greatly reducing long start-up time and wasteful active current consumption in a stand-by mode of the conventional antenna switch driver circuits. The implemented single-pole four-throw antenna switch is perfectly capable of handling a high power signal up to +35 dBm with suitably low IL of less than 1 dB, and shows second- and third-order harmonic distortion of less than -45 dBm when a 1-GHz RF signal with a power of +35 dBm and a 2-GHz RF signal with a power of +33 dBm are applied. The proposed antenna switch consumes almost no static power.</P>

        • SCISCIE

          A TV Receiver Front-End With Linearized LNA and Current-Summing Harmonic Rejection Mixer

          Im, Donggu,Lee, Ockgoo,Nam, Ilku IEEE 2017 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.64 No.3

          <P>A low-noise and highly linear wideband receiver front-end composed of the linearized low noise amplifier and current-summing harmonic rejection mixer is implemented in a 0.18-mu m CMOS process for TV tuner applications. It shows a measured voltage gain (A(v)) of more than 34.5 dB, a noise figure of less than 3.5 dB, and a third-order input-referred intercept point (IIP3) of more than -20 dBm in the frequency range from 44 to 880 MHz. The baseband coefficient scaling and summation based on the current mirror ensure a third-and fifth-harmonic rejection ratio of over 45 dBc in measurement with high linearity performance. The power consumption of the proposed TV receiver front-end is 16.2 mW at a 1.8-V supply voltage.</P>

        • A Wideband Digital TV Receiver Front-End With Noise and Distortion Cancellation

          Donggu Im,Ilku Nam IEEE 2014 IEEE transactions on circuits and systems. a publi Vol.61 No.2

          <P>A low noise and highly linear wideband CMOS receiver front-end for digital TV receivers is proposed. The proposed RF front-end comprises a wideband noise canceling common gate low noise amplifier (LNA) with a capacitively cross-coupled current source, a highly linear up-conversion micromixer with third-order intermodulation distortion cancellation, and a highly linear surface acoustic wave (SAW) driver with enhanced loop gain. The RF front-end was fabricated using a 0.13 μm CMOS process and it draws 27 mA from a 1.5 V supply voltage. It achieves a voltage gain of 23 dB, a noise figure of less than 4 dB, an IIP3 of greater than -6.5 dBm, and an IIP2 of greater than 28 dBm across the entire input band from 54 MHz to 882 MHz.</P>

        • A CMOS Resistive Feedback Differential Low-Noise Amplifier With Enhanced Loop Gain for Digital TV Tuner Applications

          Donggu Im,Hong-Teuk Kim,Kwyro Lee IEEE 2009 IEEE transactions on microwave theory and techniqu Vol.57 No.11

          <P>A resistive feedback differential low-noise amplifier (LNA) with enhanced loop gain is implemented as a part of a digital TV (DTV) tuner using a 0.18-mum CMOS process. A voltage buffer having higher gain, higher linearity, and lower noise figure (NF) than those of the conventional differential source follower (DSF), which is called the differential hybrid voltage buffer (DHVB) in this paper, is designed by combining the common source amplifier and source follower. By adopting the DHVB with optimized performance as a voltage buffer of the conventional resistive feedback differential LNA, the loop gain of the LNA can be increased. This leads to a highly linear resistive feedback LNA with higher gain and lower NF compared to the conventional resistive feedback LNA. For the wide gain range, the proposed LNA includes the variable gain function based on the resistive attenuator employing the T-switch. The measurement results of the proposed LNA exhibit a maximum gain of 16 dB and a gain range of 50 dB. At maximum gain, the LNA shows an average NF of 2.8 dB, a third-order input-referred intercept point of -1 dBm, a second-order input-referred intercept point of 40 dBm, and S11 of under -9 dB in a frequency range from 48 to 860 MHz. The power consumption is 30.6 mW at a 1.8-V power supply and the chip area is 0.25 mm<SUP>2</SUP>.</P>

        • Highly Linear Silicon-on-Insulator CMOS Digitally Programmable Capacitor Array for Tunable Antenna Matching Circuits

          Donggu Im,Kwyro Lee IEEE 2013 IEEE microwave and wireless components letters Vol.23 No.12

          <P>A stacked-FET linear 4-bit silicon-on-insulator (SOI) CMOS switched capacitor array is designed for use in tunable antenna matching circuits. A New biasing strategy without negative bias voltage is proposed to circumvent drawbacks such as digital switching noise and harmonics feed-through to the antenna. The proposed switched capacitor array shows almost identical power handling capability to that of the conventional version with negative bias voltage. Compared to other works in SOI or silicon-on-sapphire (SOS) technologies, it shows a comparable or better quality factor, tuning range, power handling capability, and harmonic distortion while consuming ultra low power.</P>

        • A Broadband CMOS RF Front-End for Universal Tuners Supporting Multi-Standard Terrestrial and Cable Broadcasts

          Donggu Im,Hongteuk Kim,Kwyro Lee IEEE 2012 IEEE journal of solid-state circuits Vol.47 No.2

          <P>A wideband CMOS highly linear and low noise RF front-end including inductor-less wideband LNA, integrated passive tunable filter, harmonic rejection mixer (HRM), and loop-through amplifier (LTA) is proposed for universal tuners. The proposed inductor-less wideband LNA shows a gain range greater than 55 dB with fine gain step less than 0.5 dB while achieving higher linearity and lower noise figure (NF), as compared with the traditional resistive/active feedback LNA through a source follower (SF). The integrated tunable filter covers the entire VHF bands without dividing the frequency range by multiple filters. By adopting tunable filter and HRM simultaneously, the overall harmonic rejection ratio (HRR) of over 65 dBc is obtained. The active feedback LTA utilizing a complementary characteristic of NMOS and PMOS is proposed for supporting multiple tuner applications. The proposed RF front-end achieves a maximum voltage gain of 42 dB, a minimum NF of 4.7 dB, and CTB and CSO of under -60 dBc. The power consumption including the LTA is 144 mW at a 1.8 V supply and the chip area is 1.43 mm<SUP>2</SUP> .</P>

        • KCI등재

          입력 - 결합 전류 제한 링 발진기와 하드웨어 효율적인 레벨 시프터를 적용한 저전력 안테나 스위치 컨트롤러 IC

          임동구(Donggu Im) 대한전자공학회 2013 전자공학회논문지 Vol.50 No.1

          이 논문에서는 (SOI) CMOS 공정을 이용한 저전력 안테나 스위치 컨트롤러 IC가 설계되었다. 제안 된 컨트롤러는 전력 수용능력과 고조파 왜곡 성능을 향상시키기 위하여 입력 신호에 따라 안테나 스위치를 구성하는 FET소자의 게이트 단자와 바디 단자에 +VDD, GND 그리고 ?VDD에 해당하는 3 가지 상태의 로직 레벨을 제공한다. 또한, 입력-결합 전류제한 링 발진기와 하드웨어 효율적인 레벨 시프터를 적용함으로서 전력소모와 하드웨어 복잡도를 크게 감소시켰다. 제안 된 회로는 +2.5 V전원을 공급받으며 송신 모드에서 135 ㎂를 소모하며 10 ㎲의 빠른 start-up 시간을 달성하였고, 전체 면적은 1.3 mm x 0.5mm로 설계되었다. In this paper, a low power antenna switch controller IC is designed using a silicon-on-insulator (SOI) CMOS technology. To improve power handling capability and harmonic distortion performance of the antenna switch, the proposed antenna switch controller provides 3-state logic level such as +VDD, GND, and ?VDD for the gate and body of switch of FETs according to decoder signal. By employing input-coupled current ring oscillator and hardware efficient level shifter, the proposed controller greatly reduces power consumption and hardware complexity. It consumes 135 ㎂ at a 2.5 V supply voltage in active mode, and occupies 1.3 mm × 0.5 mm in area. In addition, it shows fast start-up time of 10 ㎲.

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