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권원옥,박경,권혁제,윤석한,Kwon, Won-Ok,Park, Kyoung,Kwon, Hyuk-Je,Yoon, Suk-Han 대한전자공학회 2004 電子工學會論文誌-CI (Computer and Information) Vol.41 No.4
In this paper, a design and measurement method for FPGA embedded gigabit-transceiver is presented. Altera's Stratix GX device which is general purpose transceiver called GXB was used for implementing PCI Express transceiver. PCI Express is the generation high performance serial I/O bus used to interconnect peripheral devices. After GXB was set follow by PCI Express specifications, the design has been verified by timing simulation and implemented as hardware. We tested it as follow. First GXB internal digital and analog block test second GXB transmitter signal integrity test called Eye mask test, third GXB high-speed serial I/O buffer and on-chip termination test and the last GXB protocol test. This paper shows all the design and measurement procedure about FPGA embedded gigabit-transceiver. 본 논문은 FPGA 임베디드 기가비트 트랜시버의 테스트에 관한 방법과 측정 결과를 다룬다. 실험에 사용한 디바이스는 Altera 사의 Stratix GX 디바이스로 범용 고속 프로토콜을 지원하는 트랜시버(GXB)이다. 본 논문은 차세대 IO 버스로 대두되는 PCI Express 직렬 프로토콜을 GXB에 구현하였다. PCI Express 규격에 맞게 생성된 GXB 모듈은 타이밍 시뮬레이션을 거쳐 하드웨어 구현과 테스트를 수행하였다. 트랜시버 테스트 방법으로 GXB 내부 블록 테스트, GXB 신호 무결성 테스트, GXB 입출력 버퍼 및 온칩 터미네이션 테스트, GXB 프로토콜 테스트의 네 가지 검증 절차를 거쳤다. 본 논문을 통해 FPGA 임베디드 트랜시버의 설계방법과 테스트 절차, 측정 결과를 제시한다.
1Gbps 급 TCP/IP 오프로딩 엔진에서의 IP 설계
김대원(Dae Won Kim),김선욱(Sun Wook Kim),권원옥(Won Ok Kwon),김성운(Seoung Woon Kim) 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
As the network works in high speed, TCP/IP pro toe이 loads on the host CPU. Recently, TOE (TCP/IP Offload Engine) which processes TCP/IP on a network adapter instead of host CPU is rising up to the network market to solve the CPU burden. This paper is the design of TCP/IP offloading Engine in 1Gbps network. Especially, our engine is fully offloaded for TCP/IP using two embedded processor and Internet protocol also designed in hardware circuit level. In this paper, we show the hardware design of the Internet protocol and the result can show the satisfaction for 1Gbp network.
KOSMOS 마이크로 서버 고속 연결 망 제작과 IO 성능
권혁제(Hyukje Kwon),오명훈(Myeong-Hoon Oh),신지호(Ziho Shin),권원옥(Won-ok Kwon),김학영(Hag-Young Kim),강동재(Dongjae Kang) 대한전자공학회 2017 대한전자공학회 학술대회 Vol.2017 No.6
In this paper, we described the system interconnection topology of KOSMOS micro-sever and its hardware design configuration. The topology configured in KOSMOS micro-server was a folded hyper-cube with RapidIO Gen 2.1 x4 5Gbps per link One interconnection board connected to two compute boards on 4 CPUs each. We got 13.2Gbps@4MB(max)throughput and 2594us@4MB (min)latency of DMA, 3.5Gpbs@4KB (max), 227us@4KB(min) of message independing on the hop count.
메모리 연결망을 구성하기 위한 Gen-Z 프로토콜 분석
홍석빈(Seok-bin Hong),권원옥(Won-ok Kwon),오명훈(Myeong-Hoon Oh) 대한전자공학회 2019 대한전자공학회 학술대회 Vol.2019 No.6
In recent years, virtualization server technology has been developed to efficiently use a physical server. In response to these trends, there has been an increasing interest in new computer architecture to overcome memory wall problem. This paper deals with analysis of Gen-Z protocol that allows memory to be pooled. This protocol is characterized by a universal interconnect using a memory-semantic communication.
마이크로서버용 고속 패브릭 연결망을 위한 SRIO 브리지 통신 구현
오명훈(Myeong-Hoon Oh),신지호(Ziho Shin),권혁제(Hyukje Kwon),김영우(Young Woo Kim),권원옥(Won-Ok Kwon),김학영(Hag-Young Kim) 대한전자공학회 2015 대한전자공학회 학술대회 Vol.2015 No.11
In the era of cloud computing, various server systems have been introduced. A microserver, which has low-power and high-density characteristics, is known to be a novel approach of future server systems. The microserver can include multiple computing resources and, hence, a high-speed and reliable fabric interconnection among the computing resources is highly required in order to utilize those resources. In this paper, for the implementation of the fabric interconnection mentioned above, Serial RapidIO is introduced. We also address the end-point network environment and suggest the test result for feasibility on Linux operating system.