AJAX를 이용한 소방엔진펌프의 모니터링과제어 시스템 구현

양오,이헌국 한국반도체디스플레이기술학회 2016 반도체디스플레이기술학회지 Vol.15 No.3

In this paper, the fire engine pump is controlled and monitored by the AJAX (Asynchronous Javascript and Xml) in the web server. The embedded system with built-in system having a processor and a memory of high performance occurs many problems in transmitting the large amount of data in real time through the web server. The AJAX is different from HTML (Hyper Text Makeup Language) with java script technology and can make RIA (Rich Internet Application). It process the necessary data by using asynchronous and it take advantage of usefulness, accessibility, a fast response time. Using AJAX can build up web server with real time and monitoring that fire engine pump status, check processing pump memory in the event of fire, also remotely monitors can do. The web server system can control the fire engine pump as like the black box. The experimental results show the effectiveness and commercialize possibility.

FPGA를 이용한 시퀀스 제어용 32비트 마이크로프로세서 설계

양오,Yang, Oh 대한전자공학회 2003 電子工學會論文誌-SD (Semiconductor and devices) Vol.40 No.6

본 논문은 FPGA를 이용하여 시퀀스 제어용 32비트 마이크로프로세서를 설계하였다. 이를 위해 VHDL을 이용하여 톱-다운 방식으로 마이크로프로세서를 설계하였으며, 고속처리의 문제점을 해결하기 위해 프로그램 메모리부와 데이터 메모리부를 분리하여 설계함으로써 인스트럭션을 페치 하는 도중에 시퀀스 명령을 실행할 수 있는 Harvard 구조로 설계하였다. 또한 마이크로프로세서의 명령어들을 시퀀스제어에 적합하도록 RISC형태의 32 비트 명령어로 고정하여 명령어의 디코딩 시간과 데이터 메모리의 인터페이스 시간을 줄였다. 특히 설계된 마이크로프로세서의 실시간 디버깅 기능을 구현하기 위해 싱글 스텝 런, 일정 프로그램 카운터 브레이크, 데이터 메모리와 일치시 정지 기능 등을 구현함으로써 구현된 프로세서의 디버깅을 쉽게 하였다. 또한, 시퀀스제어에 적합한 펄스명령, 스텝 콘트롤 명령, 마스터 콘트롤 명령 등과 같은 비트 조작 명령과, BIN형과 BCD형 산술명령, 배럴 쉬프트명령 등을 구현하였다. 이와 같은 기능들을 FPGA로 구현하기 위하여 자이링스(Xilinx)사의 V600EHQ240(60만 게이트)과 Foundation 4.2i를 사용하여 로직을 합성하였다. Foundation 합성툴 환경에서 시뮬레이션과 실험에서 성공적으로 수행되었다. 본 논문에서 구현된 시퀀스 제어용 마이크로프로세서의 우수성을 보이기 위해 시퀀스제어용 명령어를 많이 가지고 있는 Hitachi사의 마이크로프로세서인 H8S/2148과 성능을 비교하여 본 논문에서 설계된 시퀀스 제어용 프로세서가 우수함을 확인하였다. This paper presents the design of 32 bit microprocessor for a sequence control using a field programmable gate array(FPGA). The microprocessor was designed by a VHDL with top down method, the program memory was separated from the data memory for high speed execution of sequence instructions. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 32 bits. And the real time debug operation was implemented for easeful debugging the designed processor with a single step run, PC break point run, data memory break point run. Also in this designed microprocessor, pulse instructions, step controllers, master controllers, BM and BCD type arithmetic instructions, barrel shift instructions were implemented for sequence logic control. The FPGA was synthesized under a Xilinx's Foundation 4.2i Project Manager using a V600EHQ240 which contains 600,000 gates. Finally simulation and experiment were successfully performed respectively. For showing good performance, the designed microprocessor for the sequence logic control was compared with the H8S/2148 microprocessor which contained many bit instructions for sequence logic control. The designed processor for the sequence logic showed good performance.

FPGA를 이용한 시퀀스 로직 제어용 고속 프로세서 설계

양오,Yang, Oh 대한전기학회 1999 전기학회논문지A Vol.48 No.12

This paper presents the design of high speed processor for a sequence logic control using field programmable gate array(FPGA). The sequence logic controller is widely used for automating a variety of industrial plants. The FPGA designed by VHDL consists of program and data memory interface block, input and output block, instruction fetch and decoder block, register and ALU block, program counter block, debug control block respectively. Dedicated clock inputs in the FPGA were used for high speed execution, and also the program memory was separated from the data memory for high speed execution of the sequence instructions at 40 MHz clock. Therefore it was possible that sequence instructions could be operated at the same time during the instruction fetch cycle. In order to reduce the instruction decoding time and the interface time of the data memory interface, an instruction code size was implemented by 16 bits or 32 bits respectively. And the real time debug operation was implemented for easy debugging the designed processor. This FPGA was synthesized by pASIC 2 SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to sequence control system with inputs and outputs of 256 points. The designed processor for the sequence logic was compared with the control system using the DSP(TM320C32-40MHz) and conventional PLC system. The designed processor for the sequence logic showed good performance.

PD 제어기와 신경회로망을 이용한 유도전동기의 속도제어

梁吾 대한전자공학회 2002 電子工學會論文誌-SC (System and control) Vol.39 No.3

This paper presents the implementation of the speed control system for 3 phase induction motor using PD controller and neural networks. The PD controller is used to control the motor and to train neural networks at the first time. And neural networks are widely used as controllers because of a nonlinear mapping capability, we used feedforward neural networks(FNN) in order to simply design the speed control system of the 3 phase induction motor. Neural networks are tuned online using the speed reference, actual speed measured from an encoder and control input current to motor. PD controller and neural networks are applied to the speed control system for 3 phase induction motor, are compared with PI controller through computer simulation and experiment respectively. The results are illustrated that the output of the PD controller is decreased and feedforward neural networks act main controller, and the proposed hybrid controllers show better performance than the PI controller in abrupt load variation and the precise control is possible because the steady state error can be minimized by training neural networks. 본 논문에서는 PD 제어기와 신경회로망을 이용하여 3상 유도전동기의 속도제어 시스템을 구현하고자 한다. PD 제어기는 초기의 제어를 담당하며 신경회로망의 초기 학습을 담당한다. 또한, 신경회로망은 비선형 매핑능력과 학습능력이 탁월하기 때문에 제어기로 많이 사용되며 특히 전향경로 신경망은 구조가 매우 간단하기 때문에 본 논문에서는 이를 이용하여 유도전동기의 속도제어 시스템에 구현하였다. 신경회로망의 입력으로는 모터의 기준속도, 엔코더를 이용하여 측정한 모터의 실제 속도와 제어입력 전류를 이용하였고, 온라인 상태로 학습되도록 하였다. 본 논문에서 제안된 알고리즘의 타당성을 보이기 위해 기존에 널리 사용되었던 PI 제어기와 비교평가를 하였으며 시뮬레이션과 실험결과로부터 초기운전 상태에서는 PD 제어기가 주로 제어를 담당하지만 시간이 지남에 따라 신경회로망이 학습되어 신경회로망이 주 제어기가 됨을 확인하였다. 아울러, 제안된 하이브리드 제어기가 PI 제어기보다 우수하고 특히 부하변동과 같은 외란에 강인함을 알 수 있었으며, 정상상태 오차가 현저히 감소하여 정밀한 속도제어가 가능함을 확인하였다.

신경 회로망을 이용한 3상 유도전동기의 위치 제어시스템 구현에 관한 연구

양오 청주대학교 산업과학연구소 1999 産業科學硏究 Vol.17 No.1

A PID controller has been used for industrial machine control since it has many advantages such as the simple structure and fast response. But it is difficult to find the optimal value of proportional, integral and differential gain for the PID controller and the steady state error makes the application to precision control system unsuitable. A control algorithm using Neural Networks and reaching mode controller had been proposed to solve these problems and the algorithm was implemented in this paper. DSP(TMS320C31) which is high speed processor and FPGA designed for motor control were used for the fast calculation of response, control input, PWM wave generation, and speed measurement of the induction motor. Experimentation for position control of 3 phase induction motor was executed to show superiority of this controller and the probability of application to industrial machine.

DSP를 이용한 BLDC 모터의 속도제어와 무선통신 시스템 구현

양오 청주대학교 2012 産業科學硏究 Vol.29 No.2

This paper presents the implementation for the wireless communication system and speed control of BLDC motor using a TMS320F28335 DSP. In order to implement the speed control and communication system, this paper use the TI's TMS320F28335-150MHz DSP which has 32bit Digital Signal Processing MPU, 18 PWM channels, three 32bit timers and 88 GPIO, 12-bit A/D convertors of 16 channels, 256 kbytes flash memory, 36 kbytes SRAM, 3 channels SCI(UART). Also wireless communication system using ZigBee modules between the DSP and the HMI application to a remote monitering system was implemented. The motor speed command and the parameters of anti-windup PI speed controller were modified by HMI application software via the wireless Zigbee module. Finally the experimental results show the feasibility of the control algorithm and remote control and monitoring using Zigbee communication at some factory automation driving systems.

유도전동기의 속도제어를 위한 VLSI 설계에 관한 연구

양오,유영상 청주대학교 산업과학연구소 1998 産業科學硏究 Vol.16 No.-

In this paper, We will introduce a VLSI design for the speed control of an Induction Motor that is widely used because of development of IGBT(semiconductor for high power control device), and DSP(Digital Signal Processor) nowadays. There are two ways in VLSI design, the one is that use circuit diagram, the other is that use VHDL which describes hardware. We will use the latter. The VLSI designed by us consists of a PWM wave generator which compare triangle wave with sine wave to generate PWM wave, a wait signal generator to interface I/O having slow speed to high speed DSP, a M/T speed measuring device to measure of motor speed and position, a watch dog timer to prevent system from being down, I/0 ports to control extermal input and output, LEDs, etc. This VLSI was designed and developed by using FPGA of QuickLoglc Co, which can be operated at 40MHz clock. Finally, the performance of designed VLSI will be proved by experiment it on a actual three phase induction motor drive system.

PFC 컨버터와 DTC를 이용한 BLDC 모터의 구동 시스템 구현

양오 대한전자공학회 2007 電子工學會論文誌-SC (System and control) Vol.44 No.5

본 논문에서는 일정 토크영역에서 승압형 PFC 컨버터와 직접토크제어(DTC) 방법을 사용하여 BLDC 모터의 구동 시스템을 DSP(TMS320F2812)로 구현하였다. 기존의 6단계 PWM 전류제어와 달리 미리 정한 샘플시간 마다 간단한 look-up 표로부터 2상 도통 모드에 대한 인버터의 전압 상태 벡터를 설정함으로써 원하는 전류파형을 만들었으며 이로부터 기존의 전류제어기보다 훨씬 빠른 토크 응답특성을 얻을 수 있었다. 또한 BLDC 모터의 비 이상적인 사다리형 역기전력에 의해 발생되는 저주파 토크변동을 저감하기 위하여 위치 loop-up 표를 사용하였다. 아울러 역률을 보정하기 위해 승압형 PFC 컨버터를 구성하였고 이 때 전파 정류된 입력전압과 출력전압, 인덕터의 전류에 의해 평균전류모드 제어 방식으로 80 KHz마다 PWM 듀티(duty)가 조절 되도록 하였다. 이와 같이 복잡한 제어 알고리즘은 초고속 DSP의 출현으로 PFC와 DTC 알고리즘이 동시에 제어가 가능하며, 본 논문에서는 DTC 알고리즘을 구현할 때 DSP의 일반 범용의 출력포트를 사용하여 구현하였고 단지 PFC에서만 1개의 PWM을 사용하여 디지털 제어기를 구현하였다. 실험을 통해 DTC 알고리즘과 PFC 컨버터를 이용한 BLDC 모터 구동 시스템의 타당성과 효용성을 보였고, 실험결과로부터 PFC 컨버터를 사용하지 않았을 때는 역률이 약 0.77이었으나 PFC 컨버터를 사용하였을 때는 부하변동에 관계없이 약 0.9997로 크게 향상됨을 확인하였다. In this paper, the boost Power Factor Correction (PFC) technique for Direct Torque Control (DTC) of brushless DC motor drive in the constant torque region is implemented on a TMS320F2812DSP. Unlike conventional six-step PWM current control, by properly selecting the inverter voltage space vectors of the two-phase conduction mode from a simple look-up table at a predefined sampling time, the desired quasi-square wave current is obtained, therefore a much faster torque response is achieved compared to conventional current control. Furthermore, to eliminate the low-frequency torque oscillations caused by the non-ideal trapezoidal shape of the actual back-EMF waveform of the BLDC motor, a pre-stored back-EMF versus position look-up table is designed. The duty cycle of the boost converter is determined by a control algorithm based on the input voltage, output voltage which is the dc-link of the BLDC motor drive, and inductor current using average current control method with input voltage feed-forward compensation during each sampling period of the drive system. With the emergence of high-speed digital signal processors (DSPs), both PFC and simple DTC algorithms can be executed during a single sampling period of the BLDC motor drive. In the proposed method, since no PWM algorithm is required for DTC of BLDC motor drive, only one PWM output for the boost converter with 80 kHz switching frequency is used in a TMS320F2812 DSP. The validity and effectiveness of the proposed DTC of BLDC motor drive scheme with PFC are verified through the experimental results. The test results verify that the proposed PFC for DTC of BLDC motor drive improves power factor considerably from 0.77 to as close as 0.9997 with and without load conditions.

에너지 저장시스템을 위한 납축전지의 충·방전시스템 설계

양오 청주대학교 2018 産業科學硏究 Vol.35 No.2

This paper proposes the charge and discharge system design of lead acid battery for ESS(energy storage system) which is the new renewable energy that government has recently promoted. The proposed lead acid battery charge and discharge system consists of two capacitors, a buck-boost converter, three level T-type inverter, LC filter and DC_Link stage. Using a 12V(40AH) battery per charge and discharge experiment with 25 series connections, the inverter output was 3KW and 97% efficiency at switching frequency of 16.8KHz. The experimental results show that the proposed energy storage system reaches the expected good performance.

시각동기를 위한 IRIGB 디코더 시스템 설계

양오 청주대학교 산업과학연구소 2020 産業科學硏究 Vol.37 No.2

In this paper, the IRIGB decoder system was designed for precise time synchronization. The proposed time synchronization system consists of a digital signal IRIG-B000 and an analog signal IRIG-B120 respectively. The zero crossing and comparator were used to obtain the analog time information. The IRIGB decoder system for time synchronization was designed using Altera's FPGA which is EPM570T100 and a 32bit high-performance MCU for coding to obtain precise time information. The proposed algorithms were verified through simulations and experiments respectively. Compared with the conventional time synchronization system, the proposed time synchronization system was simple in structure and had the precise 1PPS with ± 50ns for error accuracy.