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崔英奎 忠州大學校 1999 한국교통대학교 논문집 Vol.34 No.2
The merit of ASIC is to have many input and output terminals with the high density of circuits. Therefore, the current ASIC circuits are required the circuits to control various inputs and outputs. In this paper, the interface circuits of designed programmable peripheral have 3 port for 8-bit I/O. It has two modes of mode selection and single bit set/reset feature. In this paper, We have designed and verified the interface circuit of programmable peripheral unit with VHDL language and V-system tool, and systhesized in compass with the verified VHDL language. And then, we have layouted the synthesized circuit by 0.8μ standard cell method of LSI company
최영규 대한전기학회 2004 전기학회논문지C Vol.53 No.1(C)
We have carried out a basic experiment in order to develope a super high-resolution optical microscope which transcend the limitation of diffraction and the wavelength of lightwave. The image of this scope is composed by measuring the evanescent wave which is localized on the surface of the testing materials. A detecting probe was fabricated with a single mode optical fiber to be sharpened by the chemical etching, and drived by PZT. The standing wave of 0.33㎛ wavelength evanescent wave which was generated from the 0.78㎛-wavelength semiconductor laser was detected by the 0.5㎛-thickness optical fiber probe.
최영규,조남경 충주대 산업과학기술연구소 1996 産業科學論文集 Vol.4 No.-
To Implement the PLD by using EDIF netlist, which have been generally used in most CAD tools, Joined Information Extraction Algorithm which can extract Joined Information from the Joined information of the netlists and Boolean Equation Generator Algorithm is developed. In this paper the two - level boolean equation generated by using Joined Infoemation Extraction algorithm, Boolean Equation Generation algorithm is implemented by the MYPLD tools. In addition it is verifed that the result of comparing the JEDEC file of the PLD with the PALSAM tool is equivalent.