CGMI 다중칩모듈 기판 제작 ( A Fabrication of CGMI Multichip Module Substrate )

주철원,박홍옥,이상복,남기수 한국통신학회 1996 한국통신학회 학술대회논문집 Vol.15 No.3

감광성 BCB를 이용한 절연막층에서의 비아형성

주철원,임성훈,한병성 한국전기전자재료학회 2001 전기전자재료학회논문지 Vol.14 No.5

Via for achieving reliable fabrication of MCM(Multichip Module) substrate was formed on photosensitive BCB layer. The MCM substrate consists of photosensitive BCB(Benzocyclobutene) interlayer dielectric and copper conductors. In order to form the vias in the photosensitive BCB layer, the process of forming the BCB layer and its via forming plasma etch using C$_2$F$\_$6//O$_2$ gas were evaluated. The thickness of the BCB layer after hard bake was shrunk down to 40% of the original. The resolution of vias formed on the BCB was 15㎛ and the slope after develop was 85 degree. AES analysis was done on two vias, one is etched in C$_2$F$\_$6/O$_2$ gas and the other isnot etched. On the via etched in C$_2$F$\_$6//O$_2$, native C was detected and the amount of native C was reduced after Ar sputter. On the via not etched in C$_2$F$\_$6//O$_2$, organic C was detected. As a result of AES, BCB residue was not removed by Ar sputter, so plasma etch is necessary for achieving reliable vias.

패키지형태에 따른 반도체소자의 고장률예측

주철원,이상복,김성민,김경수,Ju, Cheol-Won,Lee, Sang-Bok,Kim, Seong-Min,Kim, Gyeong-Su 한국전자통신연구원 1991 전자통신동향분석 Vol.6 No.3

현재 전자장비는 대부분 반도체소자로 구성되어 있어 이들 소자의 신뢰성이 매우 중요하다. 반도체소자의 신뢰성은 고장률로 표현되는데 실질적인 고장률은 사용현장에서 수집된 데이터에서 산출되지만 데이터 수집기간이 길고, 고장원인이 불분명하며, 수적으로도 빈약한 실정이다. 따라서 본고에서는 MIL-HDBK-217E의 고장률예측 모델을 이용하여 반도체소자를 제조기술, 패키지형태, 칩접착 상태별로 구분하여 고장률을 산출하였다.

경사진 전극링을 이용한 고균일도의 미세 솔더범프 형성

주철원,이경호,민병규,김성일,이종민,강영일,Ju, Chul-Won,Lee, Kyung-Ho,Min, Byoung-Gue,Kim, Seong-Il,Lee, Jong-Min,Kang, Young-il 한국전기전자재료학회 2005 전기전자재료학회논문지 Vol.18 No.9

The plating shape in the opening of photoresist becomes gradated shape in the fountain plating system, because bubbles from the wafer surface are difficult to escape from the deep openings, vias. In this paper, the bubble flow from the wafer surface during plating process was studied and we designed the tilted electrode ring to get uniform bump height on all over the wafer and evaluated the film uniformity by SEM and $\alpha-step$. In a-step measurement, film uniformities in the fountain plating system and the tilted electrode ring contact system were $\pm16.6\%,\;\pm4\%$ respectively.

멀티칩 기술을 이용한 ATM 교환기용 Switch 모듈 제작

주철원,김창훈,한병성,Ju, Cheol-Won,Kim, Chang-Hun,Han, Byeong-Seong 대한전기학회 2000 전기학회논문지C Vol.54 No.12

We fabricated switch module of ATM(Asynchronous Transfer Mode) exchange system with MCM-C(MultiChip Module Co-fired) technology and measured its electrical characteristics. Green tape was used as substrate and Au/Ag paste was used to form the interconnect layers. The via holes were made by drill and filled with metal paste usign screen method. After manufacturing the substrate, chips and passive components were assembled on the substrate. In electrical test, the module showed the output signal of 46.9MHz synchronized with input signal. In the view of substrate size reduction, the area of MCM switch module was 35% of conventional hybrid switch module.

RF용 MCM-D 기판 내장형 인덕터

주철원,박성수,백규하,이희태,김성진,송민규 한국마이크로전자및패키징학회 2000 마이크로전자 및 패키징학회지 Vol.7 No.3

RF(radio Frequency)용 MCM(Multichip Module)-D 기판 내장형 인덕터를 개발하였다. MCM 기술은 고밀도 패키징 기술로서 주로 디지털회로에 많이 적용되어 왔으나, 최근에는 아날로그회로 및 디지털회로가 혼재된 혼성신호 및 초고주파 회로에도 적용되고 있다. 혼성신호에서는 능동소자 주변에 많은 수의 수동소자가 연결되므로 MCM-D 기판에 수동소자를 내장시키면 원가절감과 시스템의 크기 축소 및 경량화를 이를 수 있을 뿐 아니라, 성능과 신뢰성을 향상시킬 수 있다. 본 논문에서 MCM-D 기판은 Cu/감광성 BCB(Benzocyclobutene)를 각각 금속배선 및 절연막 재료로 사용하였고, 금속배선은 Ti/Cu를 각각 1000 $\AA$/3000 $\AA$으로 스퍼터한 후 fountain 방식으로 전기 도금하여 3 $\mu\textrm{m}$ Cu를 형성하였으며, 인덕터는 coplanar구조로 하여 기존의 반도체 공정을 이용하여 MCM-D기판에 인덕터를 안정적으로 내장시키고 전기적 특성을 측정하였다. We developed embedded inductors in MCM-D substrate for RF applications. The increasing demand for high density packaging was the driving forces to the development of MCM-D technology. Most of these development efforts have been focused on high performance digital circuits. However, recently there is a great need fur mixed mode circuits with a combination of digital, analog and microwave devices. Mixed mode modules often have a large number of passive components that are connected to a small number of active devices. Integration of passive components into the high density MCM substrate becomes desirable to further reduce cost, size, and weight of electronic systems while improving their performance and reliability. The proposed MCM-D substrate was based on Cu/photosensitive BCB multilayer and Ti/Cu is used to form the interconnect layer. Seed metal was formed with 1000 $\AA$ Ti/3000 $\AA$ Cu by sputtering method and main metal was formed with 3 $\mu\textrm{m}$ Cu by electrical plating method. The multi-turn sprial inductors were designed in coplanar fashion. This paper describe the manufacturing process of integrated inductors in MCM-D substrate and the results of electrical performance test.

플립칩용 웨이퍼레벨 Fine Pitch 솔더범프 형성

주철원,김성진,백규하,이희태,한병성,박성수,강영일 한국전기전자재료학회 2001 전기전자재료학회논문지 Vol.14 No.11

Solder bump was electroplated on wafer for flip chip application. The process is as follows. Ti/Cu were sputtered and thick PR was formed by several coating PR layer. Fine pitch vias were opened using via mask and then Cu stud and solder bump were electroplated. Finally solder bump was formed by reflow process. In this paper, we opened 40㎛ vias on 57㎛ thick PR layer and electroplated solder bump with 70㎛ height and 40㎛ diameter. After reflow process, we could form solder bump with 53㎛ height and 43㎛ diameter. In plating process, we improved the plating uniformity within 3% by using ring contact instead of conventional multi-point contact.

A Flip-Chip-Packaged InP HBT Transimpedance Amplifier for 40-Gb/s Optical Link Applications

주철원,Jong-Min Lee,민병규,Kyung-Ho Lee,김성일 한국물리학회 2007 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.50 No.3

A 40-Gb/s transimpedance amplifier was designed and fabricated with InP/InGaAs heterojunction bipolar transistor (HBT) technology. In this study, we interconnect a 40-Gbps transimpedance amplifier to a duroid substrate by flip-chip bonding instead of conventional wire bonding for the interconnection. For the flip-chip bonding, we developed a fine pitch bump with a 70-$\mu$m diameter and a 150-$\mu$m pitch by using a wafer level package (WLP) process. To study the effect of the WLP, we measured and analyzed the electrical performances in the wafer and in the package module using the WLP. The small signal gains in the wafer and in the package module were 7.24 dB and 6.93 dB, respectively. The difference in the small signal gain between the wafer and the package module was 0.31 dB. This small difference in gain was due to the short interconnection length obtained by using the bump. The return loss was under --10 dB in both the wafer and the module. Thus, the WLP process can be used for millimeter wave GaAs microwave monolithic integrated circuits (MMICs) with a fine pitch pad, and a duroid substrate can be used in the flip-chip bonding process.

MCM-D 기판 내장형 수동소자 제조공정

주철원,이영민,이상복,현석봉,박성수,송민규 한국마이크로전자및패키징학회 1999 마이크로전자 및 패키징학회지 Vol.6 No.4

MCM-D 기판에 수동소자를 내장시키는 공정을 개발하였다. MCM-D 기판은 Cu/감광성 BCB를 각각 금속배선 및 절연막 재료로 사용하였고, 금속배선은 Ti/cu를 각각 1000$\AA$/3000$\AA$으로 스퍼터한 후 fountain 방식으로 전기 도금하여 3 um Cu를 형성하였으며, BCB 층에 신뢰성있는 비아형성을 위하여 BCB의 공정특성과 $C_2F_6$를 사용한 플라즈마 cleaning영향을 AES로 분석하였다. 이 실험에서 제작한 MCM-D 기판은 절연막과 금속배선 층이 각각 5개, 4개 층으로 구성되는데 저항은 2번째 절연막 위에 thermal evaporator 방식으로 NiCr을 600$\AA$증착하여 시트저항이 21 $\Omega$/sq가 되게 형성하였고. 인덕터는 coplanar 구조로 3, 4번째 금속배선층에 형성하였으며, 커패시터는 절연막으로 PECVD $Si_3N_4$를 900$\AA$증착한 후 1, 2번째 금속배선층에 형성하여 88nF/$\textrm {cm}^2$의 커패시턴스를 얻었다. 이 공정은 PECVD $Si_3N_4$와 thermal evaporation NiCr 공정을 이용함으로써 기존의 반도체 공정을 이용하여 MCM-D 기판에 수동소자를 안정적으로 내장시킬 수 있었다. We developed Fabrication process of embedded passive components in MCM-D substrate. The proposed MCM-D substrate is based on Cu/photosensitive BCB multilayer. The substrate used is Si wafer and Ti/cu metallization is used to form the interconnect layer. Interconnect layers are formed with 1000$\AA$ Ti/3000$\AA$ Cu by sputtering method and 3$\mu\textrm{m}$ Cu by electrical plating method. In order to form the vias in photosensitive BCB layer, the process of BCB and plasma etch using $C_2F_6$ gas were evaluated. The MCM-D substrate is composed of 5 dielectric layers and 4 interconnect layers. Embedded resistors are made with NiCr and implemented on the $2^{nd}$ dielectric layer. The sheet resistance of NiCr is controlled to be about 21 $\Omega$/sq at the thickness of 600$\AA$. The multi-turn sprial inductors are designed in coplanar fashion on the $4^{th}$ interconnect layer with an underpass from the center to outside using the lower $3^{rd}$ interconnect layer. Capacitors are designed and realized between $1^{st}$ interconnect layer and $2^{nd}$ interconnect layer. An important issue in capacitor is the accurate determination of the dielectric thickness. We use the 900$\AA$ thickness of PECVD silicon nitride film as dielectric. Capacitance per unit area is about 88nF/$\textrm {cm}^2$at the thickness of 900$\AA$. The advantage of this integration process is the compatibility with the conventional semiconductor process due to low temperature PECVD silicon nitride process and thermal evaporation NiCr process.

EM시험에서의 Joule Heating 영향 및 초기저항값

朱哲源(Chul Won Ju),姜亨坤(Hyung Gon Kang),韓秉誠(Byung Sung Han) 대한전기학회 1999 전기학회논문지C Vol.48 No.6