영상의 QoS를 고려한 DCT의 중간결과값 연산모델 ( An Imprecise Computation Model for DCT Considering QoS )

임강빈,신준호,정진군,최경희,정기현 대한전자공학회 1996 대한전자공학회 학술대회 Vol.1996 No.7

Trapping Efficiency of a Femtosecond Laser and Damage Thresholds for Biological Cells

임강빈,김법민,진단,박화준,김수기,한수민,주성빈 한국물리학회 2006 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.48 No.5I

Microparticles, including biological cells, are trapped and manipulated using continuous wave (CW) and femtosecond laser tweezers. Although the difference in the optical trapping efficiencies of the CW laser tweezers and the femtosecond laser tweezers is not very large, the difference increases as the particle size decreases perhaps because of potential self-focusing of the femtosecond pulses. In addition, white damage spots are generated near the focus during the femtosecond laser trapping of biological cells even at extremely low average powers. The instantaneous optical damage thresholds were measured as a function of trap depth. These results may be useful in optimizing the optical trapping of biological cells when using femtosecond lasers.

PIMODS서버에서 분산 비디오스트림의 전송을 위한 상호연결망

임강빈,류문간,신준호,김상중,최경희,정기현 대한전자공학회 1999 電子工學會論文誌, C Vol.c36 No.11

본 논문은 멀티미디어 서버의 부하 편중현상을 해결하기 위한 스위치를 제시하고 그 스위치에서의 트래픽 특성 분석을 위한 간단한 확률적 모델을 제안한다. 스위치는 경로설정 방안으로 우회방안을 이용하므로 스위치 내의 트래픽 부하는 우회확률에 커다란 영향을 미친다 본 논문에서는 제안한 모델에 의거하여 스위치의 트래픽 부하에 따르는 우회확률을 추적하였다. 그리고 그 결과를 실험적 결과와 비교함으로써 확률적 모델의 타당성을 검증하였다. 확률적 모델에 의하여 스위치 안으로 유입되는 패킷의 양에 따라 발생하는 우회와 그에 따르는 스위치의 트래픽 포화지점을 예측할 수 있다. This paper presents an interconnection network for load balancing on a multimedia server and proposes a simple probabilistic model of the interconnection network for analysing the traffic characteristics. Because the switch uses deflection algorithm for routing, the traffic load on the switch seriously affects deflection probability. In this paper, we trace the deflection probability as a function of the traffic load according to the model. By comparing the result with the empirical result, we prove that the model is useful for estimating the deflection probability and traffic saturation point against the amount of packets getting into the switch.

네트워크 시스템의 세션 관리 부하를 감쇄하기 위한 사건 기반 타임아웃 정책

임강빈,최창석,문종욱,정기현,최경희,Yim, Kang-bin,Choi, Chang-seok,Moon, Jong-wook,Jung, Gi-hyun,Choi, Kyung-hee 한국정보처리학회 2004 정보처리학회논문지 A Vol.11 No.2

방화벽이나 침입탐지시스템과 같은 세션 관리를 요하는 시스템은 관리하는 세션 테이블의 크기가 증가함에 따라 각 세션에 대한 타임아웃 처리 시 발생하는 오버헤드가 커지게 된다. 본 논문은 기존의 타이머를 이용한 시간 기반 타임아웃 관리 방법에 비하여 시스템의 부하를 현저히 감쇄하여 네트워크 시스템의 패킷 처리량을 증가시킬 수 있는 사건 기반 타임아웃 관리 방법을 제안한다. 또한, 실제 구현한 시스템을 이용한 실험을 통하여 제안한 방법이 기존의 방법에 비하여 보다 많은 패킷을 처리할 수 있음을 확인한다. The session management overhead on the network systems like firewalls or intrusion detection systems is getting grown as the session table is glowing. In this paper. we propose the event-based timeout management policy to increase packet processing throughput on network systems by decreasing the system's timeout management overhead that is comparable to the existing time-based timeout management policies. Through some empirical studies using a session management system implemented in this paper we probed that the proposed policy provides better packet processing throughput than the existing policies.

A Coop Project-based Business Engineers' Model for Regional Universities Running ABEEK Program

임강빈,조대철,이해각,Yim, Kang-Bin,Cho, Dae-Chul,Lee, Hae-Kag 한국실천공학교육학회 2011 실천공학교육논문지 Vol.3 No.1

This paper suggests a realistic, business engineers' model based on Coop projects run by regional universities or colleges, in which students must meet the guidelines for engineering design that ABEEK requires. Many of current activities such as Coop programs and Internships aimed for engineering majored-undergraduates have notled them either to a satisfactory level of business skill at entrepreneur side, or to their higher chance of employment opportunities. Under the circumstances like this, we need a revised version of Coop activities: for example, launching a project that will be fully supported intrust by both sides, and thus improving students' business skill while they are working on that project. We demonstrate in this study how students have greatly improved their business skill through a model project that was planned by a working group, was successfully carried out on real job positions, and many of the students in the working group were job-offered finally as this new model suggested.

예측 가능한 고속 인터럽트 디스패칭 방안

임강빈 순천향대학교 부설 산업기술연구소 2003 순천향 산업기술연구소논문집 Vol.9 No.1

In this paper I propose a policy to compensate for a substantial drawback of the non-vectored interrupt mechanism generally adopted by the contemporary RISC microprocessors. Through an empirical study I verify the enhancement on performance of the proposed policy by comparing the interrupt response times before and after the policy is applied. The interrupt response time is considered as one of the most important factors for the real-time systems and should be minimized for the fast response of the real-time tasks in the multi-tasking environments. Especially, the variation of the interrupt response time should be within a limited boundary to support the predictability of the real-time operating systems. Many contemporary RISC microprocessors gave up the vectored interrupt mechanism at a cost of the structural simplification and the operational consistency. Instead, they take the interrupt in a single interrupt handler and dispatch it by the software to the dedicated service routine to the appropriate priority. Typical interrupt dispatch mechanism checks out each bit in the interrupt event flag register and causes a drastic increment of the response time according to the decrement of the interrupt priority. The interrupt handler implemented in this paper provides a fast dispatch operation by using a hashing mechanism indexing a small priority table using the content of the interrupt event flag register. Additionally it can support the predictability required by the real-time operating systems by reducing the difference variation of the interrupt response times among the different priorities.

군집모델 기반 사물인터넷 이상 행위 탐지 및 제어 플랫폼 개발

임강빈,고영건,김찬민,배도현,백상훈,서주영,정택준 순천향대학교 부설 산업기술연구소 2019 순천향 산업기술연구소논문집 Vol.25 No.1

As a number of practical applications have been realized in artificial intelligence and big data area along with a cluster network composed of a large number of Internet of Things devices, the types of attacks also have been becoming diverse. If an IoT device in a cluster network is attacked by a malicious user, a large number of devices can not perform normal operations and are exposed to various risks. In this paper, we implemented a surveillance server monitoring IoT devices and visualizing the behavioral data from the devices in real time to predict and respond to the threats.

네트워크 프로세서를 위한 다중 쓰레드 스케줄링

임강빈,박준구,정기현,최경희,Yim, Kang-Bin,Park, Jun-Ku,Jung, Gi-Hyun,Choi, Kyung-Hee 한국정보처리학회 2004 정보처리학회논문지 C : 정보통신,정보보안 Vol.11 No.3

본 논문은 다중 프로세서(Multiprocessor) 기반 다중 쓰레드(Multithreaded) 구조의 네트워크 프로세서를 이용한 패킷 치리 시스템에서 패킷을 보다 고속으로 처리하기 위한 쓰레드 스케줄링 기법을 제안한다 이를 위하여 스케줄링과 관련한 인자를 실험을 통하여 얻고, 패킷 내용 및 다중 쓰레드 아키텍쳐를 표현하는 인자를 포함하도록 설계하였다. 시뮬레이터를 이용한 실험을 통하여 제안된 스케줄링 기법이 제공하는 처리율 및 부하 분산 정도가 다른 스케줄링 기법과 비교하여 효율적임을 증명하였다. In this paper, we propose a thread scheduling algorithm for faster packet processing on the network processors with multithreaded multiprocessor architecture. To implement the proposed algorithm. we derived several basic parameters related to the thread scheduling and included a new parameter representing the packet contents and the multithreaded architecture. Through the empirical study using a simulator, we proved the proposed scheduling algorithm provides better throughput and load balancing compared to the general thread scheduling algorithm.

고속 병렬 패킷 여과를 위한 효율적인 단일버퍼 관리 방안

임강빈,박준구,최경희,정기현 대한전자공학회 2004 電子工學會論文誌-TC (Telecommunications) Vol.41 No.7

본 논문은 고속의 병렬 패킷 여과를 위한 다중프로세서 시스템이 가지는 단일 버퍼에서 단일 버퍼의 판독을 위한 다중프로세서 간의 경합을 중재하기 위한 효율적인 단일 버퍼 관리 방안을 제안하고 이를 실제의 다중 프로세서 시스템에 적용하여 실험함으로써 제안한 방안이 납득할 만한 성능을 제공함을 증명하였다. 병렬 패킷 여과시스템으로는 처리의 고속화를 위하여 패킷 여과규칙을 다중의 프로세서에 걸쳐 분산 처리하는 경우를 모델로 정하였다. 실제의 실험은 다중 프로세서를 가지는 네트워크 프로세서에서 이루어졌으며 100Mbps 의 통신망을 배경으로 하였다. 제안한 방안의 성능을 고찰하기 위하여 프로세서 수의 변화 및 여과 규칙의 처리 시간의 변화 등에 따르는 실제 패킷 전송률을 측정하였다. This paper proposes an efficient centralized sin91e buffer management algorithm to arbitrate access contention mon processors on the multi-processor system for high-speed Packet filtering and proves that the algorithm provides reasonable performance by implementing it and applying it to a real multi-processor system. The multi-processor system for parallel packet filtering is modeled based on a network processor to distribute the packet filtering rules throughout the processors to speed up the filtering. In this paper we changed the number of processors and the processing time of the filtering rules as variables and measured the packet transfer rates to investigate the performance of the proposed algorithm.

중간 결과값 연산 모델을 위한 2차원 DCT 구조

임강빈,정진군,신준호,최경희,정기현 대한전자공학회 1997 電子工學會論文誌, C Vol.c34 No.9

This paper proposes an imprecise compuitation model for DCT considering QOS of images and a two dimensional DCT architecture for imprecise computations. In case that many processes are scheduling in a hard real time system, the system resources are shared among them. Thus all processes can not be allocated enough system resources (such as processing power and communication bandwidth). The imprecise computtion model can be used to provide scheduling flexibility and various QOS(quality of service)levels, to enhance fault tolerance, and to ensure service continuity in rela time systems. The DCT(discrete cosine transform) is known as one of popular image data compression techniques and adopted in JPEG and MPEG algorithms since the DCT can remove the spatial redundancy of 2-D image data efficiently. Even though many commercial data compression VLSI chips include the DCST hardware, the DCT computation is still a very time-consuming process and a lot of hardware resources are required for the DCT implementation. In this paper the DCT procedure is re-analyzed to fit to imprecise computation model. The test image is simulated on teh base of this model, and the computation time and the quality of restored image are studied. The row-column algorithm is used ot fit the proposed imprecise computation DCT which supports pipeline operatiions by pixel unit, various QOS levels and low speed stroage devices. The architecture has reduced I/O bandwidth which could make its implementation feasible in VLSI. The architecture is proved using a VHDL simulator in architecture level.