http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
윤성대 釜山工業大學校 1993 論文集 Vol.35 No.-
This paper propose the dataflow architecture that can execute the vactor computation efficiently, using the early synchronization and constructing the frame memory and it's controller for the vec-tor computation. So the architecture conquest the defect of the general dataflow machine. It is shown the organization of weight adjust problem in a neural network.
윤성대 釜山工業大學 1987 論文集 Vol.29 No.-
This paper analyzws a few methods for control folw complexity metric of a program and proposes a new algorithm that analyzws control flow using CNT included their characteristic. To certify the accuracy, simulate a general program using thealgorithm. And it's algorithm provides information of all paths forthe path testing.
金鍾晋,尹成大 釜山工業大學校 1992 論文集 Vol.34 No.-
We proposed a class of topology for message-passing architectures which have a several requirements postulated in the design of a massively parallel distributed system in VLSI/WSI application. XMESH topology has a extreme regularity and symmetry structure. It also has a very small diameter and average distance, many alternate paths between nodes and simple routing algorithm.
윤성대 釜山工業大學校 1986 論文集 Vol.28 No.2
In this paper, the algorithm for conver ting a sequential program to a parallel program by analyzing data flow has been presented. An algorithm was used too check the number of segmentations and to determine their execu-tion priority. In terms of this algorithm, the execution times of the sequential program could be shortened by turning on the cross-bar wsitches between processors and memories. By running a simulation program in FORTRAN, the corrections of algorithms was con-firmed and the execution times of several program were compared with those of correspond-ing sequential programs. In the statement containing an arithmetic expressions, the execution time is shortened by pipe line.
벡타 연산을 효율적으로 수행하기 위한 다중 스레드 구조
윤성대,정기동,Yun, Seong-Dae,Jeong, Gi-Dong 한국정보처리학회 1995 정보처리논문지 Vol.2 No.6
본 논문에서는 벡타연산을 효율적으로 수행하고 대단위 병렬시스템을 지원하는 다중 스레드구조, MULVEC(MULtithreaded architecture of the VEctor Computations) 을 제시한다. MULVEC은 데이타플로우 모델에 수퍼 스칼라 RISC 마이크로 프로세서를 갖는 기존의 폰 노이만 모델을 도입하였다. 그리고 동일한 스레드 세그멘트내에 벡타 연산이 반복되는 경우에 상태필드를 이용하여 동기화의 수를 감축시켰으며, 이에 의해 문맥전환 횟수, 통신량 등을 감소시켰다. 그리고 노드 수의 변화에 대한 MULVEC의 성능평가(프로그램들의 수행시간, 프로세서들의 이용율)와 *T의 성능평가(프로그램의 수행시간)를 SPARC station 20 (super scalar RISC microprocessor)에서 시뮬레이션을 하였으며, 노드의 수, 루프의 반복홋수 등에 따라 프로그램의 수행시간이 MULVEC이 *T보 다 약 1-2배 정도 빠르다는 것을 알 수 있었다. This paper presents a design of a high performance MULVEC (MULtithreaded architecture for the VEctor Computations), as a building block of massively parallel Processing systems. The MULVEC comes from the synthesis of the dataflow model and the extant super sclar RISC microprocesso r. The MULVEC reduces, using status fields, the number of synchronizations in the case of repeated vector computations within the same thread segment, and also reduces the amount of the context switching, network traffic, etc. After be nchmark programs are simulated on the SPARC station 20(super scalar RISC microprocessor)the performance (execution time of programs and the utilization of processors) of MULVEC and the performance(execution time of a program) of *Taccording the different numbers of node are analyzed. We observed that the execution time of the program in MULVEC is faster than that in * T about 1-2 times according the number of nodes and the number of the repetitions of the loop.