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박정순(Park Jeong Soon),임재혁(Jae Hyuk Lim),엄윤용(Youn Young Earmme),임세영(Seyoung Im) 대한기계학회 2005 대한기계학회 춘추학술대회 Vol.2005 No.11
Chip crack analysis is conducted for multichip package subject to molding process and thermal cycling test using finite element method. We investigate the effect of initial vertical crack length on energy release rates of the system, and evaluate the maximum allowable crack length under pressure during molding process. In thermal-cycling test, an initial delamination is assumed between the second chip and a barrier tape, which is located under the second chip. The effect of material properties and multichip geometries on delamination are clarified.
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임재혁(Jae Hyuk Lim),한만희(Man-Hee Han),이준연(Jun-Youn Lee),박정순(Jeong Soon Park),엄윤용(Youn Young Earmme),임세영(Seyoung Im) 대한기계학회 2005 대한기계학회 춘추학술대회 Vol.2005 No.11
Prediction of warpage and residual stress in semiconductor chip devices play an important role in chip design. However, there are a few uncertainties in warpage prediction due to unknown patterning material properties, and moisture effect on polymer film. To estimate patterning material properties, we adopt a composite plate analysis and experimental techniques. and measure the warpage of chip after drying at about 250℃ for 30min to remove moisture. In 100㎛, 80㎛ chip cases, finite element analysis result shows a good agreement with measured values, but for 50㎛ and 60㎛ chip cases, there exist a substantial deviation from the measured values due to local deformation from imperfection and defects inherently embedded in the patterning layer and nonuniform bonding between PIcoating and silicon.
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