Hybrid Monte Carlo 시뮬레이션에 대한 InAlAs / InGaAs HBT 의 전자전송 해석

송정근,황성범,이경락 ( Chung Kun Song,Sung Bum Hwang,Kyung Lack Lee ) 한국전기전자재료학회 1997 전기전자재료학회논문지 Vol.10 No.9

반도체 트랩전하를 활용하여 뉴런의 활동전위 발생을 모방한 뉴리스터 소자의 이론적 고찰

송정근(Chung Kun Song) 대한전자공학회 2021 전자공학회논문지 Vol.58 No.11

본 논문은 뉴로몰픽 컴퓨터의 핵심소자로 사용할 수 있는 뉴리스터(Neuristor)에 관한 것으로 특히 뉴런의 활동전위 펄스발생 동작을 모방하는 것을 특징으로 하는 뉴리스터의 해석적 모델을 제시한다. 본 모델에서는 반도체 트랩의 전자 충돌이온화와 전자포획에 의한 공간전하 형성 및 소멸의 시간적 변화, 그리고 공간전하의 유도전계에 의한 전류의 급격한 시간적 증감에 의한 전류펄스 발생을 묘사하는 해석적 수식을 도출하였다. 본 뉴리스터는 바이어스 전압이 인가된 상태에서 전류펄스를 지속적으로 생성하고, 펄스 주파수는 바이어스 전압에 대해서 시그모이드 관계를 나타냄으로써 뉴런의 활동전위 펄스와 유사한 동작을 나타낸다. 시뮬레이션 결과 실리콘 반도체에서 에너지 준위가 0.5 eV되는 트랩 불순물(O, Fe)을 10<SUP>17 </SUP>cm<SUP>-3</SUP> 농도로 도핑하고, 실리콘-전극 계면에 쇼트키 장벽 에너지 0.5 eV 형성하는 전극재료(Ni, Sb)를 사용하면 동작전압 2V에서 뉴런의 동작을 모방하는 뉴리스터를 구현할 수 있다. This paper is regarding to a semiconductor neuristor characterized by mimicking the generation of the action potentials of neuron, especially to the analytical model to describe the generation of the neuron-like current pulses. In this model the mathematical expressions were derived to express the generation of current pulses under a bias voltage by analyzing the time variation of space charge produced by impact ionization of electrons on traps in semiconductor and the time variation of the injection current caused by the space-charge-induced electric field at the contact. According to simulation, it was identified that the neuristor operating with the bias voltage of 2 V can be realized by doping the deep impurities such as O or Fe into silicon with the trap energy of 0.5 eV and the density of 10<SUP>17</SUP> cm<SUP>-3</SUP>, together with the Schottky contact such as Ni or Sb having the barrier energy of 0.5 eV to Si semiconductor. The neuristor can be considered as a core device for neuromorphic computer.

Organic Vapor Phase Deposition 방식을 이용한 펜타센 유기박막트랜지스터의 제작

정보철,송정근,Jung Bo-Chul,Song Chung-Kun 한국전기전자재료학회 2006 전기전자재료학회논문지 Vol.19 No.6

In this paper, we investigated the deposition of pentacene thin film on a large area substrate by Organic Vapor Phase Deposition(OVPD) and applied it to fabrication of Organic Thin Film Transistor(OTFT). We extracted the optimum deposition conditions such as evaporation temperature of $260^{\circ}C$, carrier gas flow rate of 10 sccm and chamber vacuum pressure of 0.1 torr. We fabricated 72 OTFTs on the 4 inch size Si Wafer, Which produced the average mobility of $0.1{\pm}0.021cm^2/V{\cdot}s$, average subthreshold slope of 1.04 dec/V, average threshold voltage of -6.55 V, and off-state current is $0.973pA/{\mu}m$. The overall performance of pentacene TFTs over 4 ' wafer exhibited the uniformity with the variation less than 20 %. This proves that OVPD is a suitable methode for the deposition of organic thin film over a large area substrate.

스크린 인쇄와 리버스 오프셋 인쇄를 혼합한 대면적 미세 전극용 인쇄공정

박지은,송정근,Park, Ji-Eun,Song, Chung-Kun 한국전기전자재료학회 2011 전기전자재료학회논문지 Vol.24 No.5

In this paper a printing process for patterning electrodes on large area substrate was developed by combining screen printing with reverse off-set printing. Ag ink was uniformly coated by screen printing. And then etching resist (ER) was patterned in the Ag film by reverse off-set printing, and then the non-desired Ag film was etched off by etchant. Finally, the ER was stripped-off to obtain the final Ag patterns. We extracted the suitable conditions of reverse Using the process we successfully fabricated gate electrodes and scan bus lines of OTFT-backplane used for e-paper, in which the diagonal size was 6 inch, the resolution $320{\times}240$, the minimum line width 30 um, and sheet resistance 1 ${\Omega}/{\Box}$.

잉크젯 방식으로 PVP 뱅크와 TIPS-펜타센 반도체 층을 제작한 유기 박막트랜지스터

김세민,박종승,송정근,Kim, Se-Min,Park, Jong-Seung,Song, Chung-Kun 한국전기전자재료학회 2009 전기전자재료학회논문지 Vol.22 No.11

We investigated the influence of organic solvents on the droplet properties of 6,13-bis (triisopropylsilylethynyl) pentacene (TIPS-pentacene), which was used for semiconductor of organic thin film transistors (OTFTs) and deposited by ink jet printing. From the result of the investigation, the conditions of a suitable solvent is that boiling point should be above $200^{\circ}C$ to reduce coffee stain and the surface tension above 32 dyn/cm to decrease the droplet size. Consequently, we selected tetralin which have a high boiling point ($207^{\circ}C$) and high surface tension (34.3 dyn/cm) as the solvent for TIPS-pentacene, and applied it to OTFTs. In fabrication process the conventional bank process employing photolithography and etching process was replaced by ink jet printed bank process, resulting in simplifying the process. Especially, polyvinylphenol was used for the bank, and the high hydrophobicity could improve the confinement of TIPS molecules inside the bank, enhancing the performance over the conventional hydrophilic polyvinylalcohol bank. The mobility was $0.18\;cm^2/Vs$, current on/off ratio $2.09{\times}10^5$, subthreshold slope 0.42 V/dec, and off state current $0.049\;pA/{\mu}m$.

은 잉크를 이용한 그라비아 오프셋의 전극인쇄에서 닥터링 공정의 영향

최기성,박진석,송정근,Choi, Ki Seong,Park, Jin Seok,Song, Chung-Kun 한국전기전자재료학회 2013 전기전자재료학회논문지 Vol.26 No.6

In this paper, we analyzed the effects of doctoring process on the patterns of Ag ink in gravure off-set printing. The parameters of doctoring process were the angle and the pressure, which was represented by the depth of blade movement to the gravure roll, of doctor blade to the surface of gravure roll, and the angle of patterns engraved on the gravure roll to the doctor blade moving direction. The proper parameters were extracted for the fine patterns and they were 15 mm for the pressure, $60^{\circ}$ for the blade angle. And the angle of patterns with respect to the blade movement should be less than $40^{\circ}$ for the best results. The gravure off-set printing with the above parameters was carried out to print gate electrodes and scan bus lines of OTFT-backplane for e-paper. The line width of $50{\mu}m$ was successfully obtained. The thickness of electrodes was $2.5{\mu}m$ and the surface roughness was $0.65{\mu}m$ and the sheet resistance was $15.8{\Omega}/{\Box}$.

TIPS-pentacene의 잉크젯 인쇄공정에서 액적의 수와 기판 온도에 따른 OTFTs의 전계이동도 변화

권동훈,박진석,송정근,Kwon, Dong-Hoon,Park, Jin Seok,Song, Chung-Kun 한국전기전자재료학회 2013 전기전자재료학회논문지 Vol.26 No.6

In this paper, we analyzed the effects of the number of TIPS-pentacene droplets and also the substrate temperature on the performance of OTFTs. As the number of the droplets increased, the mobility increased and reached the peak value and then reduced at the all temperatures. The peak mobility was $0.14{\pm}0.03cm^2/V{\cdot}sec$ at 3 droplets and $41^{\circ}C$, $0.19{\pm}0.02cm^2/V{\cdot}sec$ at 4 droplets and $46^{\circ}C$, and $0.35{\pm}0.10cm^2/V{\cdot}sec$ at 7 droplets and $51^{\circ}C$. The reason of existence of peak mobility can be found in matching the evaporation of solvent with the velocity of crystal formation. When two parameters were properly matched, the mobility produced the highest.

Ag 잉크의 미세접촉인쇄에 있어서 동역학적 파라미터가 인쇄특성에 미치는 영향 분석

박성률(Sung-Ryool Park),송정근(Chung-Kun Song) 대한전자공학회 2010 電子工學會論文誌-SD (Semiconductor and devices) Vol.47 No.2

본 논문에서는 금속 전극을 미세접촉인쇄방식으로 Ag ink를 이용하여 제작하는데 있어서 접착속도, 분리속도, 접촉시간의 세 가지의 동역학적 파라미터가 잉크 전이율에 미치는 영향을 분석하여 최적의 공정조건을 도출하였다. 잉킹공정에서는 접촉속도는 1 ㎜/s 이하, 접촉 후 유지시간은 짧게 하며, 분리속도는 1000 ㎜/s로 빠르게 해야 잉크의 전이율이 98%이상 높았다. 프린팅 공정에서는 반대로 접촉속도는 100㎜/s 이상의 빠르게, 접촉 후 유지시간은 30초 이상, 분리속도는 1㎜/s 이하로 느리게 할 때 최고의 인쇄특성을 보였다. 이를 이용해 전체 5㎝×5㎝ 면적에 최소 선폭 30㎛, 두께는 300~500㎚, 50㎚이하의 약 15~16μΩ ? ㎝ 비저항을 가지는 전극을 인쇄하였다. This paper describes the effects of kinetic parameters such as attaching speed, attaching time, and dettaching speed on printing property of electrodes which were fabricated by micro-contact printing with Ag ink. In inking process the attaching speed was preferable to be less than 1 ㎜/s, attaching time as short as possible, and detaching speed larger than 1000 ㎜/s in order to obtain the transfer ratio of ink larger than 98%. Meanwhile in printing process the parameters were totally opposite to the results of inking process; attaching speed larger than 100 ㎜/s, attaching time larger than 30 sec, and detaching speed less than 1 ㎜/s for the best results. With the parameters we could obtain the micro-contact printed electrodes with the minimum line width of 30 ㎛, thickness of 300 ~500 ㎚, roughness less than 50 ㎚, and resistivity of about 15~16 μΩ?㎝.

펜타센 TFT와 유기 LED로 구성된 픽셀 어레이 제작

최기범,류기성,정현,송정근,Choe Ki Beom,Ryu Gi Seong,Jung Hyun,Song Chung Kun 대한전자공학회 2005 電子工學會論文誌-SD (Semiconductor and devices) Vol.42 No.12

본 논문에서는 Poly-ethylene-terephthalate (PET) 기판 위에 Organic Thin Film Transistor (OTFT)와 Organic Light Emitting Diode (OLED)를 직렬 연결시킨 픽셀과 64 x 64 픽셀로 구성된 어레이를 제작하여 동작을 시연하였다. OTFT는 PET 기판과의 호환성을 고려하여 Poly 4-vinylphenol을 게이트 절연체로, 펜타센을 활성층으로 사용하여 제작되었다. 개별 소자 수준에서는 이동도가 $1.0\;cm^2/V{\cdot}sec$로 나타났으나, 어레이에서는 $0.1\~0.2\;cm^2/V{\cdot}sec$로 약 10배 정도 감소하였다. 어레이의 동작을 분석하였고 OTFT의 OLED에 대한 전류구동능력을 확인하였다. In this paper, we fabricated a pixel array in which each pixel was consisted of Organic Thin Film Transistor (OTFT) serially connected with Organic Light Emitting Diode (OLED) on Poly-ethylene-terephthalate (PET) substrate and the number of pixels was 64 x 64. As a gate insulator of OTFT, the thermally cross-linked PVP was used and the organic semiconductor, Pentacene, is deposited for an active layer of OTFT considering the compatibility with PET substrate. The mobility of OTFT is $1.0\;cm^2/V{\cdot}sec$ as a discrete device, but it was reduced to $0.1\~0.2\;cm^2/V{\codt}sec$ in the array. We analyzed the operation of the array and confirmed the current driving ability of OTFTs for the OLEDs.

펜타센 TFT를 이용한 AMOLED 픽셀회로 설계

류기성,최기범,이명원,송정근,Ryu Gi-Seong,Choe Ki-Beom,Lee Myung-Won,Song Chung-Kun 대한전자공학회 2006 電子工學會論文誌-SD (Semiconductor and devices) Vol.43 No.6

본 논문에서는 OTFT를 기반으로 하는 AMOLED 디스플레이 구현을 위해 두 개의 OTFT와 하나의 캐패시터 그리고 하나의 OLED로 구성된 화소 회로를 설계하였고 그 동작을 시뮬레이션을 통하여 분석하였다. 먼저, 화소 회로를 이론적으로 설계하였고, $32\times32$ AMOLED 패널을 제작하기 위한 화소의 Layout을 설계하고 TFT W/L과 저장 캐패시터의 용량을 설계하였다. 그리고 설계된 화소 회로의 전기적 특성을 분석하기 위해 HSPICE 시뮬레이션 하였다 시뮬레이션 결과 OTFT 기반의 AMOLED 구현 가능성을 확인하였다. In this paper, we designed a pixel circuit for AMOLED display based on organic thin film transistors and analyzed the operation with SPICE simulation. First, we theoretically designed the pixel circuit with the result of layout for fabricating $32\times32$ AMOLED panel, TFT W/L and capacitance of storage capacitor. And we simulated the designed pixel circuit using HSPICE for analyzing electrical performance. As a result of simulation, we identified the possibility of AMOLED display based on OTFTs.