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높은 정확도의 3차원 대칭 커패시터를 가진 보정기법을 사용하지 않는 14비트 70MS/s 0.13um CMOS 파이프라인 A/D 변환기
문경준,이승훈,이경훈 대한전자공학회 2006 電子工學會論文誌-SD (Semiconductor and devices) Vol.43 No.12
This work proposes a calibration-free 14b 70MS/s 0.13um CMOS ADC for high-performance integrated systems such as WLAN and high-definition video systems simultaneously requiring high resolution, low power, and small size at high speed. The proposed ADC employs signal insensitive 3-D fully symmetric layout techniques in two MDACs for high matching accuracy without any calibration. A three-stage pipeline architecture minimizes power consumption and chip area at the target resolution and sampling rate. The input SHA with a controlled trans-conductance ratio of two amplifier stages simultaneously achieves high gain and high phase margin with gate-bootstrapped sampling switches for 14b input accuracy at the Nyquist frequency. A back-end sub-ranging flash ADC with open-loop offset cancellation and interpolation achieves 6b accuracy at 70MS/s. Low-noise current and voltage references are employed on chip with optional off-chip reference voltages. The prototype ADC implemented in a 0.13um CMOS is based on a 0.35um minimum channel length for 2.5V applications. The measured DNL and INL are within 0.65LSB and 1.80LSB, respectively. The prototype ADC shows maximum SNDR and SFDR of 66dB and 81dB and a power consumption of 235mW at 70MS/s. The active die area is 3.3mm2. 본 설계에서는 무선 랜 등 최첨단 무선 통신 및 고급영상 처리 시스템과 같이 고해상도와 높은 신호처리속도, 저전력 및 소면적을 동시에 요구하는 고성능 집적시스템 응용을 위해 기존의 보정기법을 사용하지 않는 14b 70MS/s 0.13um CMOS A/D 변환기 (Analog-to-Digital Converter : ADC)를 제안한다. 제안하는 ADC는 중요한 커패시터 열에 인접신호에 덜 민감한 3차원 완전 대칭 구조의 레이아웃 기법으로 소자 부정합에 의한 영향을 최소화하였고, 3단 파이프라인 구조로 고해상도와 높은 신호처리속도와 함께 전력 소모 및 면적을 최적화하였다. 입력단 SHA 회로에는 Nyquist 입력에서도 14비트 이상의 정확도로 신호를 샘플링하기 위해 게이트-부트스트래핑 (gate-bootstrapping) 회로를 적용함과 동시에 트랜스컨덕턴스 비율을 적절히 조정한 2단 증폭기를 사용하여 14비트에 필요한 높은 DC 전압 이득을 얻음과 동시에 충분한 위상 여유를 갖도록 하였으며, 최종단 6b flash ADC에는 6비트 정확도 구현을 위해 2단 오픈-루프 오프셋 샘플링 기법을 적용하였으며, 기준 전류 및 전압 발생기는 온-칩으로 집적하여 잡음을 최소화하면서 필요시 선택적으로 다른 크기의 기준 전압 값을 외부에서 인가할 수 있도록 하였다. 제안하는 시제품 ADC는 0.13um CMOS 공정으로 요구되는 2.5V 전원 전압 인가를 위해 최소 채널길이는 0.35um를 사용하여 제작되었으며, 측정된 DNL 및 INL은 14비트 해상도에서 각각 0.65LSB, 1.80LSB의 수준을 보이며, 70MS/s의 샘플링 속도에서 최대 SNDR 및 SFDR은 각각 66dB, 81dB를 보여준다. 시제품 ADC의 칩 면적은 3.3mm이며 전력 소모는 2.5V 전원 전압에서 235mW이다.
문경준,박준호,황기현,이화석,김형수 대한전기학회 2006 Journal of Electrical Engineering & Technology Vol.1 No.4
This paper presents an application of the parallel Adaptive Evolutionary Algorithm (AEA)to search an optimal solution of the service restoration in electric power distribution systems, which is occurs, to restore as much load as possible by transferring the de-energized load in the out of service area via network reconfiguration to the appropriate adjacent feeders at minimum operational cost without violating operating constraints. This problem has many constraints and it is very dificult to find the optimal solution because of its numerous local minima. In this investigation, a parallel AEA was developed for the service restoration of the distribution systems. In parallel AEA, a genetic algorithm (GA) and an evolution strategy (ES) in an adaptive manner are used in order to combine the merits of two diferent evolutionary algorithms: the global search capability of the GA and the local search capability of the ES. In the reproduction procedure, proportions of the population by GA and ES are adaptively modulated according to the fitness. After AEA operations, the best solutions of AEA processors are transferred to the neighboring processors. For parallel computing, a PC cluster system consisting of 8 PCs was developed. Each PC employs the 2 GHz Pentium CPU and is conected Ⅳdeveloped algorithm has been tested with a practical distribution system in Korea. From the simulation results, the proposed method found the optimal service restoration strategy. The obtained results were the same as that of the explicit exhaustive search method. Also, it is found that the proposed algorithm is efficient and robust for service restoration of distribution systems in terms of solution quality, speedup, efficiency, and computation time.
Antioxidant Effects of Statins in Patients with Atherosclerotic Cerebrovascular Disease
문경준,김석재,조연희,류수경,방오영 대한신경과학회 2014 Journal of Clinical Neurology Vol.10 No.2
Background and Purpose Oxidative stress is involved in the pathophysiological mechanisms of stroke (e.g., atherosclerosis) and brain injury after ischemic stroke. Statins, which inhibit 3-hydroxy-3-methylglutaryl coenzyme A (HMG-CoA) reductase, have both pleiotropicand low-density lipoprotein (LDL)-lowering properties. Recent trials have shown that highdose statins reduce the risk of cerebrovascular events. However, there is a paucity of data regarding the changes in the oxidative stress markers in patients with atherosclerotic stroke afterstatin use. This study evaluated changes in oxidative stress markers after short-term use of ahigh-dose statin in patients with atherosclerotic stroke. Methods Rosuvastatin was administered at a dose of 20 mg/day to 99 patients who had suffered an atherosclerotic stroke and no prior statin use. Blood samples were collected before and1 month after dosing, and the serum levels of four oxidative stress markers–malondialdehyde(MDA), oxidized LDL (oxLDL), protein carbonyl content (PCO), and 8-hydroxy-2’-deoxyguanosine (8-OHdG)–were evaluated to determine the oxidation of MDA and lipids, proteins,and DNA, respectively, at both of those time points. Results The baseline levels and the degrees of reduction after statin use differed among theoxidative stress markers measured. MDA and PCO levels were associated with infarct volumeson diffusion-weighted imaging (r=0.551, p<0.05, and r=0.444, p=0.05, respectively). Statin usedecreased MDA and oxLDL levels (both p<0.05) but not the PCO or 8-OHdG level. While thereduction in MDA levels after statin use was not associated with changes in cholesterol, that inoxLDL levels was proportional to the reductions in cholesterol (r=0.479, p<0.01), LDL(r=0.459, p<0.01), and apolipoprotein B (r=0.444, p<0.05). Conclusions The impact of individual oxidative stress markers differs with time after ischemic stroke, suggesting that different oxidative markers reflect different aspects of oxidativestress. In addition, short-term use of a statin exerts antioxidant effects against lipid peroxidationvia lipid-lowering-dependent and -independent mechanisms, but not against protein or DNAoxidation in atherosclerotic stroke patients.
양성자가속기 연구센터 전력계통 운용을 위한 제어논리 구성 방안
문경준(Kyeong-Jun Mun),박성식(Sungsik Park),전계포(Gye Po Jeon),조진삼(Jin Sam Cho),민의섭(Yi-Sub Min),남정민(Jungmin Nam),김준연(Jun Yeon Kim) 대한전기학회 2010 대한전기학회 학술대회 논문집 Vol.2010 No.7
본 논문에서는 현재 경주시 건천읍에 설계중인 양성자가속기 연구센터의 전력공급을 위해 154㎸ 수전설비를 설계 중에 있다. 이러한 전력계통 운용시에는 전력계통 내의 다수의 계전기, 차단기 및 경보신호가 동작하며, 해당 경보에 대해 고장진단 및 고장차단을 위한 제어논리 수립이 필수적이다. 따라서 본 논문에서는 양성자가속기 연구센터 전력계통 각 구성별로 계전기, 차단기 및 경보신호를 이용한 제어논리 수립방법을 제시함으로써 고장 및 경보를 확인할 수 있도록 하였으며, 향후 이를 활용한 전력계통 고장진단 수행시 이를 활용하고자 한다.