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김신택,민형복 대한전자공학회 1995 전자공학회논문지-A Vol.32 No.4
Fault simulators are used for accurate evaluation of fault coverages of digital circuits. But fault simulation becomes time and memory consuming job because computation time is proportional to wquare of size of circuits. Recently, several approximate algorithms for testability analysis have been published to cope with the problems. COP is very fast but cannot be used for sequential circuits, while STAFAN can ve used for sequential circuits but requires large amount of computation because it utilizes logic simulation results. In this paper EXTASEC(An Extension of Testability Analysis for Sequential Circuits) is proposed. It is an extension of COP in the sense that it is the same as COP for combinational circuits, but it can handle sequential circuits, Xicontrollability and backward line analysis are key concept for EXTASEC. Performance of EXTASEC is proven by comparing EXTASEC with a falut simulator, STAFAN, and COP for ISCAS circuits, and the result is demonstated.
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팩시밀리의 主機板에 對한 技能的 試驗機의 設計 및 具現
김신택,이재훈,김명선,김한상,민형복 成均館大學校 科學技術硏究所 1992 論文集 Vol.43 No.2
본 연구는 팩시밀리의 주기판(main board)을 기능적으로 테스트하기 위해 구현한 FFTS(Functional Facsimile Test System)에 대한 기술이다. 본 연구의 목적은, 테스트시 수반되는 모든 작업을 자동화하고, 테스트 수행중 발생하는 여러가지 상태들을 자료화하는 것이다. 아울러 주기판에 대한 입출력 신호들의 종류와 그 특성들이 변경될 경우라도 소프트웨어의 수정만으로 그 것에 대처한 후 계속적으로 테스트를 수행할 수 있도록 한다. FFTS는 주기판에 접속되는 여러가지 장치들을 하드웨어적으로 에물레이션하며, 테스트용 전용언어, 그리고 그것에 대한 컴파일러를 포함한다. FFTS로 테스트를 수행하는 방법에는 대화식 모드(IAT)와 대화식 테스트에서 수행할 수 있는 모든 과정을 테스트용 언어로 저장한 후 그것을 반복하여 사용하는 배치 모드(Batch mode) 등이 있다. FFTS의 유용성을 실증하기 위해 여러 종류의 팩시밀리에 대하여 실험을 실시하였다. FFTS (Functional Facsimile Test System) is designed and implemented. It is possible to eliminate repeated test work and to analyze the data obtained through test. If the specification of the signals from/to main board of facsmile is changed, it is possible to cope with the change by modification of FFTS software. FFTS emulates the devices connected to the main board. FFTS is designed to test the main board either by using interactive(IAT) mode with graphic user interface or by using noninteractive(NIAT) mode with test command file which is coded manually or created from IAT mode. The operation of the FITS is verified for several types of main board of G3 class facsmiles.
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김신택,강창수,전창호 한양대학교 공학기술연구소 1994 공학기술논문집 Vol.3 No.1
Parallel, hence high speed, data transfer is possible with disk arrays on which files are interleaved on many disks. For disk arrays where data are interleaved in block units, the size of a block is a major performance parameter. Therefore it is important to find an optimal block size in order to maximize the bandwidth of disk arrays. In this paper, we analyze the effects of workload, disk parameters, and the number of disks on the block size. Based on the analysis, we present a method to find an optimal block size for a disk array.
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플립플롭의 초기화 가능성을 고려한 디지탈 회로에 대한 고장 검출율의 평가 기법
민형복,김신택,이재훈 대한전자공학회 1998 電子工學會論文誌, C Vol.c35 No.4
Fault simulatior has been used to compute exact fault coverages of test vectors for digial circuits. But it is time consuming because execution time is proportional to square of circuit size. Recently, several algorithms for testability analysis have been published to cope with these problems. COP is very fast and accurate but cannot be used for sequential circuits, while STAFAN can be used for sequential circuits but needs vast amount of execution time due to good circuit simulation. We proposed EXTASEC which gave fast and accurate fault coverage. But it shows noticeable errors for a few sequential circuits. In this paper, it is shown that the inaccuracy is due to uninitializble flipflops, and we propose ITEM to improve the EXTASEC algorithm. ITEM is an improved evaluation method of fault coverage by analysis of backward lines and uninitializable flipflops. It is expected to perform efficiently for very large circuits where execution time is critical.
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김명선,김신택,민형복 成均館大學校 科學技術硏究所 1994 論文集 Vol.45 No.2
Fault coverage evaluated by fault simulators is accurate. However, fault simulation is not only memory consuming but also time consuming, and fault simulation time is propotional to, at least, square of circuit size. These limitations become more serious because of increased circuit densities. Recently, several algorithms for testability measures have been published. In this paper, three algorithms, STAFAN, COP, and PREDICT, are compared each other with respect to accuracy and execution time, in order to provide a useful guideline for those who plan to design a new digital circuit.
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조병관,김신택,조현찬,Jo, Byeong-Gwan,Kim, Sin-Taek,Jo, Hyeon-Chan 대한기계학회 2002 大韓機械學會論文集A Vol.26 No.5
In general, jerk phenomenon appeared because of gear changing, when a vehicle starts off or climbs an incline. Therefore, it makes ride quality worse. In this paper, an optimal pattern of automatic transmission was designed using fuzzy logic in order to improve ride quality. After del eloping fuzzy rule for shift pattern control of automatic transmission, dynamic characteristics (i.e. acceleration, velocity, distance and so on) were simulated using dynamic model of a car. To do this he powertrain model of a vehicle with automatic transmission including torque converter, gear box, and final gear drive - from engine to tire - is developed.
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플립플롭의 초기화 가능성을 고려한 디지털 회로에 대한 고장 검출율의 평가 기법
閔炯福,李宰勳,金信澤 성균관대학교 1998 학술회의지원논문목록집 Vol.1998 No.-
디지탈 회로의 검사 신호에 대한 고장 검출율을 정확하게 계산하기 위해 결함 시뮬레이터를 사용한다. 그러나 결함 시뮬레이터의 실행 시간은 회로를 구성하는 게이트 수의 제곱에 비례하여 오늘날의 대규모 회로에서는 많은 CPU 시간을 소모한다. 따라서 정확도는 떨어지지만 비교적 짧은 시간 안에 회로의 검사성을 평가하기 위한 검사성 분석 알고리즘이 제안되었다. COP는 빠르고 정확하느 순차회로에 적용할 수 없으며 STAFAN은 순차회로에 적용이 가능하지만 정상 회로 시뮬레이션의 사용으로 실행시간이 많이 소모된다. 본 저자들은 정확한 고장 검출율을 단시간에 얻기 위해서 EXTASEC을 제안한 바 있다. EXTASEC은 극히 일부 회로에서 정확도가 떨어지는 현상이 발생하였으며, 이 논문에서는 EXTASEC의 문제가 플립플롭의 초기화와 관련이 있는 것을 밝히고, 개선된 알고리즘 ITEM을 제안한다. ITEM은 후진선의 반복적 계산과 초기화되지 않는 플립플롭에 대한 분석으로 고장 검출율을 정확하고 빠르게 얻을 수가 있었다. Fault simulator has been used 10 compute exact Fault coverages of test vectors lor digital circuit. But it is time consuming because execution time is proportional to square of circuit size. Recently, several algorithms for testability analysis have been published to cope with these problems. COP iS very fast and accurate but cannot be used for sequential circuits, while STAFAN can be used for sequential circuits but nerds vast amount of execution time due to good circuit simulation. We proposed EXTASEC which gave fast and accurate fault coverage. But it shows noticeable errors fora few sequential circuits. In this paper, it 1s shown that the inaccuracy is due to uninitializable flipflops, and we propose ITEM to improve the EXTASEC algorithm. ITEM iS an improved evaluation method of fault coverage by analysis of backward lines and uninitializable flipflops. It is expected to perform efficiently for very large circuits where execution time is critical.
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