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고전압 비휘발성 메모리 Programming Pin ESD 개선방안에 관한 연구
권순엽(Soon-Yeob Kwon),임경식(Kyoung-Sik Im),고재혁(Jae-Hyok Ko),정신영(Shin-Young Chung),김요정(Yo-Joung Kim),박무근(Moo-Keun Park),이경진(Kyoung-Jin Lee),공배선(Bai-Sun Kong) 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
Ths paper presents a method of improving the ESD characteristic of high voltage non-volatile memory (NVM) programming pin in a 130㎚/30V technology. Suggested scheme can provide not only a major current discharge path to protect the internal circuit from ESD damage but also a voltage clamping function to prevent the soft error of programmed data during an ESD event. Resistance value of 120 ㏀ and capacitance value of 6.8㎊ were chosen for maximizing the improvement of voltage characteristic and delay time, while minimizing the area overhead. The proposed scheme has been validated by TCAD simulation and actuality silicone.