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고귀한(Gwi-Han Go),정기상(Ki-Sang Jung),김강직(Kang-Jik Kim),조성익(Seong-Ik Cho) 대한전기학회 2012 전기학회논문지 Vol.61 No.11
This paper is proposed all digital wide?range clock and data recovery circuit. The Proposed clock data recovery circuit is possible input data rate which is suggested is wide-range that extends from 100Mb/s to 3Gb/s and used an phase error detector which can use a way of over-sampling a data by using a 1/2-rate multi-phase clock and phase rotator which is regular size per 2π/16 and can make a phase rotation. So it could make the phase rotating in range of input data rate. Also all circuit is designed as a digital which has a specificity against a noise. This circuit is designed to 0.13㎛ CMOS process and verified simulation to spectre tool.