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In based on the development of communication technology, everyday life, a community, and the communication of nations is being changed to a high y information society which has simultaneous a zone of life. But, communication networks presently have many problems to satisfy new communication service required for 21 century because telephone network, data communication network, CATV network, and broadcasting network have been differently constructed. Therefore, a study on the development of application software is necessary for the early construction of B-ISDN, which efficiently satisfy the desire of users about a high information society. In this paper, we developes the service program and database of computer network and tests it through a high speed information communication network.
Synchronization system is divided into two parts, acquisition system and code tracking system. Acquisition system is to find the start time of transmission PN code when receiving is started and then code tracking system is adjusted the synchronization by moving of the receiver. In this thesis, digital PN code tracking system designed with Verilog-HDL is fully integrated using Chip Compiler tool of COMPASS adopting 0.8μm Cell-Based librBry, performs the operation of code tracking using digital delay lock loop method.
In this paper, It is proposed the automatic inspection system that detects the insertion error of parts from input image of PCB(Printed Circuit Board) bottom. After preprocessing from input image, It is set specifications of presoldering test The recognition process is performed by reference image method to testing image from original image. It results that 98% recognition rate is obtained from 100 test sample in the process of calculating 9 average feature vectors by utilizing PC8 error detecting algorithm. If the error classification and high speed testing algorithm are applied, It is anticipated that implement of system for the optimum PCB error detecting.
In this thesis, Adaptive Predictor has been designed based on the CCITT standard 32 kbps ADPCM algorithm. Designed Adaptive Predictor could calculate through the fixed -point evaluation deciding the exact prediction signal attaining the improved processing speed characteristic. Hardware has been designed with the COMPASS design tool adopting 1.0[μm] CMOS design rule. For the verification of designed hardware, the results of the logic simulation has been compared with that of the algorithm simulation followed by the coincided results with the processing time characteristic of 2(μσ). According to this result, ADPCM system could be able to process the speech signal within 4(μs) and to multiplex PCM channel property.
In this thesis, the digital filter for speech signal processing which can select and restore speech band frequency suitable for CCITT specification G.711 on transmitter-receiver in digital communication system was designed, and the digital filter was synthesized by elliptic function after the determination of design specification. To design the hardware of digital filter for speech signal processing DF(Digital Filter)block which is core block was composed of satisfying design specification. And the peripheral circuit was designed dividing the hardware into AAF(Anti Aliasing Filter), A/D converter(Analog to Digital converter), D/A converter(Digital to Analog converter), SMF(Smoothing Filter) block, and was designed on One-chip ASIC(Application Specification Integrated Circuits) using 1,2μm CMOS device which have a low-dissipation power characteristics and ease in high integration.
The inclination in a short-distance communication network and multimedia communication is required high speed A/D(analog to digital) or D/A(digital to analog) converter. Though data processing process high speed in system, if the performance of converter is non-superiority, the performance of total system is not improvement of performance. Therefore, in this paper, the proposed method reduce system H/W, compressing rate and increase system processing speed because the proposed sampling frequency method used this converter dependent not in the prime clock frequency but in input data frequency. This method is used Auto-Tracing concept and proper for multimedia communication using moving picture, speech and requiremented data A/D, D/A converting.
Semiconductor device needs the ASIC design of sophisticated technique which could implement various kinds of chip for specified application corresponding with customer's desire rather than device processing technique. Among ASIC design methods, standard cell scheme is divided into poly cell and building block method by layout technique. Building block method is the one which combinates several cell after height and width of cell. In this paper, to design standard cell of DRAM peripheral circuits, it was designed memory cell of 1-T3R, 1-capacitor structure with 1.5(μm) CMOS desist rule of 2-metal. 1-poly process. And then it was suitably designed peripheral circuits, namely, address select block and data sensing block using building block method.
The currents and load voltage of a 2-branch resistance-Inductance parallel circuit controlled by an SCR pair in the supply line are deduced. while the SCRs are nonconducting, current decays exponentially around the load loop. The extinction angle is a transcendental function of the load impedances and the supply voltage. There is close agreement between measured and calculated results. The system cannot be analyzed in terms of a single-impedance eguivalent load.