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A mobile channel model is a set of mathematical expressions into which channel characteristics obtained from field measurements can be inserted. This is done in order to predict the potential performance of a proposed mobile communication system. The basis for a medel may be either theoretical or empirical, or a combination of these two. In this paper propagation models be modeled and compared in the mobile-radio channel for indoor environment.
A solution to the real-time requirements of digital signal processing is the use of special-purpose architecture. This paper proposes a high performance VLSI architecture for three-dimensional (3-D) digital filter. The architecture is based upon a regular computational structure obtained from a state space model. The variables are as-signed to minimaize the off-chip data communicaiton requirements. Also, this paper describes a processor architecture which uses multiple arithmetic units for high throughput and system configurations for real-time implementation.
Advances in VLSI technology make it feasible to design and implement computer systems consisting of a large number of functional units. A high performance VLSI architecture for one-dimensional(1-D) digital filter applications is presented in this paper. The development of the processor architecture is based upon an algorithm decomposition scheme which increases parallelism with minimum data communication requirements. This architecture uses multiple processing units in order to achieve very high throughput. The individual processors are programmable which provides for a wide range of applications and they can be cascaded to implement a very high order system.
The throughput requirement for two-dimensioinal(2-D) digital filter is such that multiple processing units are essential for real-time implementation. Advances in VLSI technology make it feasible to design and implement computer systems consisting of a large number of functional units. The development of a very high throughput processor architecture for 2-D digital filter is based upon an algorithm decomposition scheme which minimizes data communication requirements. In this paper, a new single chip processor architecture for real-time 2-D digital signal processing applications are presented. This architecture extends the concept of using a single processing unit to the use of multiple processing units. Because this architecture has an advantage that the complexity and the number of computations per input does not increase as the size of 2-D input data increases, it can process a very large 2-D data efficiently in a near real-time.
Korean industrial situations are very rapidly changing. Sophisticate pattern of industry is resulting in the numbers and kind of workers who are need in industry. The more sophisticated the industry, the more crucial the technician's role. In order to educated electronic techician necessary to the electronic industrial society during the short period of two year course of jonior technical college, this paper suggest the educational method and curriculum which are proper to the requirement of radically developing electronic industry. In undertaking the construction of this curriculum for electronic technology based upon job analysis and studying a curriculums, this curriculum promote a good all-round education & trainning in electronic technology which will be enable to find empolyment in a wide variety of positions in electronic industry. This paper look into the problems of the junior technical college and suggest directions method for improvement of the junior technical college education.
A New procedure for handing retransmission in a selective-repeat ARQ system is proposed in this paper. This procedure can operate with a receive buffer of minimal size, in addition it place a little computational load on the transmit and receive processors. The procedure is simple enough that its throughput can be calculated exactly. Analysis of this strategy show that 1) it yields higher throughput than earlier ARQ techniques, 2) its throughput differs a little from channel capacity, for modest receive bugger size, 3) throughput approaches channel capacity, as buffer size increases. The final chapter of the paper considers the performance of ARQ system on channels in which errors in bursts. It indicates that, error burstiness has a little effect on throughput on resonable good channels.
The digital ladder structures have the desirable coefficient sensitivity and could be implented with low coefficient word lengths. In this paper the concept of a generalized delay unitis introduced and a method is developed for delay-free canonical digital realization of on arbitary reactance function. This method is on alternative approach and a generalization to the problem of digital L-C ladder structures. A specific set of constraints are imposed to satisfy the realizability. Finally an example is taken to examplity the design method.
Degradation is generated by digitalization or transmission of data. And its essential cause is noise. Therefore, researches for wavelet-based methods which reconstruct signal degraded by noise have continued. In AWGN environment, the general trend for denoising is to use the thresholding method. These methods only consider statistical characteristic regarding noise reconstructed signal includes a lot of noise because. In this paper, we present a new method which uses the cumulation of wavelet detail coefficients. As a result, reconstruction of edges and denoising performance are improved. Also we compare existing methods using SNR as the standard of judgement of improvemental effect.
The design of single phase power factor correction using a digital single processor is proposed in this paper. The digital single processor requires the A/D sampling values for line input voltage to realize the proposed power factor correction converter. The sampling values contain a high frequency noise and switching ripple due to switching noise. The A/D converter of digital single processor are started using the prediction algorithm. It is shown that the power factor is 0.99 at wide input voltage from the experiment results. The parameters and gains of PI controllers are controlled by serial communication. Also it is shown that the implemented power factor correction converter can achieve feasibility and the usefulness.