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Design of a system board of a workstation employing a 32-bit RISC Microprocessor
Lee, Jong Ick,Lee, Moon Key THE RESEARCH INSTITUTE OF ASIC DESIGN YONSEI UNIVE 1996 Journal of the Research Institute of ASIC Design Vol.3 No.1
This paper presents a system board of a workstation employing SPARK microprocessor. The SPARK is the family name of the RISC microprocessors developed in the Research Institute of ASIC Design, at Yonsei Univ.. The SPARK employed in this board system is a 32-bit RISC microprocessor which has a 46-instruction set and a 136-register file with an overlapped window architecture, adopting a 4-depth pipeline technique. Its maximum operating clock frequency is 40 MHz which is comparable to that of CY7C601-a microprocessor produced in Cypress Semiconductor Co., USA. The system board is composed of an integer unit(IU), a cache controller(CC), a Memory Mangagement Unit(MMU), a system bus, an FPU, a DMA controller, a DRAM controller and 6 I/O controllers. To accomodate the operating clock frequency of 40 MHz of the integer unit, the system bus has employed the protocols of Sbus version B.0. The devices connected to the system bus access the main memory vis DVMA. To verify their functions and timings, the devices on the path along which user programs are most likely to be executed were modeled with Verilog-HDL and simulated with Verilog-HDL simulator.
Reconfigurable Address Collector and Flying Cache Simulator
Yoon, Hyung-Min,Park, Gi-Ho,Lee, Jang-Su,Lee, Kil-Whan,Han, Tack-Don,Kim, Shin-Dug,Yang, Sung-Bong THE RESEARCH INSTITUTE OF ASIC DESIGN YONSEI UNIVE 1997 Journal of the Research Institute of ASIC Design Vol.4 No.1
Trace-driven simulation is widely used to evaluate the cache memory system. The accuracy of the trace-driven simulation depends on the accuracy and length of the trace data. To get the accurate and long trace, a trace collection hardware is designed. Flying cache simulator is attached to the tracing system to simulate various cache systems during the execution of an application program. Tracing system designed, called Reconfigurable Address Collector and Flying Cache Simulator(RACFCS), can generate the accurate and long traces and simulate cache system for the long execution time that cannot be tried to simulate by any other tracing techniques.
A Design of Programmable Fast Charge Controller for Li-Ion Battery
Lee, Chang-Wha,Lee, Suk-Ho,Kim, Su-Ki THE RESEARCH INSTITUTE OF ASIC DESIGN YONSEI UNIVE 1999 Journal of the Research Institute of ASIC Design Vol.6 No.1
This paper presents a new approach for Li-Ion rechargeable battery controllers. Instead of using 8-b microcontroller(e.g. PI16/17 series) implementation we propose hard-wired implementation. We use an EPROM for the parameter programmable function. So without microcontroller we can get microcontroller's flexibility and we can achieve small chip area. Because the charging circuit operates in noisy environment we propose noise immune algorithm in our design. We choose a time-division charging algorithm for simple application circuits avoiding a existing patent issues. To shorten the design and debugging cycle all the digital block are coded with Verilog HDL.
Design of PN Code Acquisition System with a Shared Architecture for CDMA PCS Mobile Station
Lee, Seongjoo,Lee, Janghee,Kim, Jaeseok THE RESEARCH INSTITUTE OF ASIC DESIGN YONSEI UNIVE 1999 Journal of the Research Institute of ASIC Design Vol.6 No.1
In this paper, we propose a new architecture of the PN code acquisition system which has some shared hardware blocks in order to reduce the hardware complexity. The proposed system has an energy calculation block which is shared by two active correlators. Our system is designed suitable for IS-95 based CDMA PCS. The new architecture was designed and simulated using VHDL. The gate count is about 7,500. Our proposed architecture is also useful for multi-carrier system which uses the multiple searcher.
Design of A Viterbi Decoder for Satellite Communication
Han, Jung-Il,Choi, Jong-Moon,Choi, Woo-Young,Kim, Bong-Ryul THE RESEARCH INSTITUTE OF ASIC DESIGN YONSEI UNIVE 1997 Journal of the Research Institute of ASIC Design Vol.4 No.1
In this paper, we proposed a Viterbi decoder for practical implementation of Forward Error Correction(FEC). The design was mainly focused on real-time processing by using the memory organization and its control method with constraint length 7, coding rate 1/2, Management of memory contents in a Viterbi decoder is a major design problem for both hardware and software realization. In this design, we solved that problem with sequence processing. The design was done with a standard 0.6 μm CMOS process and 2-layer metal technology. It is composed of logic circuit with 15,887 gates. It runs on a 3.3 V supply and operates at 20 MHz. The estimated power consumption is about 98 mW and the chip size is about 4 ㎜ x 4 ㎜.
Behavioral Modeling of Transport Layer Demultiplexer for HDTV
Kim, Yong-un,Kwak, Sung-ho,Yang, Hun-mo,Lee, Moon-key THE RESEARCH INSTITUTE OF ASIC DESIGN YONSEI UNIVE 1997 Journal of the Research Institute of ASIC Design Vol.4 No.1
In this paper, we designed the demultiplexer for transport packet of HDTV. Receiving the compressed and multiplexed audio, video, and auxiliary data from channel decoder, designed module can produce pure data to each decoder. These outputs may be put to audio decoder, video decoder and other predefined decoder. To support various multiplex format for the transport packet of HDTV, demultiplexer consists of sync-detector, link-header processor, adaptation-header processor, pid-comparator, cc-value comparator, and PSI processor. We have designed and simulated these modules with Verilog-HDL on behavioral level.
Geometry Accelerator for Goraud Shading Algorithms
Jeong, Cheol-ho,Park, Woo-chan,Yang, Jin-ki,Kim, Shin-Dug,Han, Tack-don THE RESEARCH INSTITUTE OF ASIC DESIGN YONSEI UNIVE 1999 Journal of the Research Institute of ASIC Design Vol.6 No.1
In this paper, the analysis of data processing method and the amount of computation in the whole geometry processing are described step by step. Floating-point ALU design is based on the characteristics of geometry processing operation. The performance of the devised ALU fitting with the geometry processing operation is analyzed by simulation after the description of the proposed ALU and geometry processor. The ALU designed in the paper can perform three types of floating-point operations simultaneously-addition/subtraction, multiplication, and division. As a result, 23.5% of performance improvement is achieved by that floating-point ALU for the whole geometry processing and another 23% of performance gain with adding area-performance efficient SRT divisor in the floating-point division and square root operation.
A Design of Data Bus Architecture for Processor-Memory Integration
Kim, Won-Tae,Kwak, Seung-Ho,Lee, Moon-Key THE RESEARCH INSTITUTE OF ASIC DESIGN YONSEI UNIVE 1999 Journal of the Research Institute of ASIC Design Vol.6 No.1
This paper presents internal data bus architecture and interconnection between internal memory and CPU as a design process of CPU-DRAM integration architecture. Internal memory constitutes four 2MB-memory banks. Data in internal memory are transferred to CPU through Memory Buffer Block (will be referred as MBB) and 128-bit internal data bus and interleaved into 32-bit format. Memory Write Buffer(will be referred as MWB) stores data delivered from CPU and writes to Memory Read Buffer (will be referred as MBB), internal memory, External Interface Block (will be referred as EIB) and MRB classifies data from MWB data and internal memory data for update and stores updated data. Buffers in MBB controls 128-bit data flow in memory bus to communicate CPU with 32-bit format. Memory Buffer of MBB and internal memory puts together with 40㎒ MCLK, Internal clock.
An On-chip Multiprocessor microprocessor with Shared MMU and Cache
Lee, Yong-hwan,Jeong, Woo-kyeong,Lee, Yong-surk THE RESEARCH INSTITUTE OF ASIC DESIGN YONSEI UNIVE 1997 Journal of the Research Institute of ASIC Design Vol.4 No.1
A multiprocessor microprocessor named SMPC (scaleable multiprocessor chip) that contains two IU(integer unit) is presented in this paper. It can execute multiple instructions from several tasks exploiting task-level parallelism that is free from intstruction dependencies, and provide high performance and throughput on both single program and multiprogramming environment. The IU is a 32-bit scalar processor especially designed to boost up the performance of string manipulations which are frequently used in RDBMS(relational data base management system) applications. A memory management unit and a data cache shared by two IUs improve the performance and reduce the chip area required. The SMPC is implemented in VLSI circuit by custom design and automated design tools.
Content Addressable Memory for CAM Module Generator
Kim, Geun-Hoe,Seo, Kwang-Soo,Lee, Moon-Key THE RESEARCH INSTITUTE OF ASIC DESIGN YONSEI UNIVE 1996 Journal of the Research Institute of ASIC Design Vol.3 No.1
This paper describes the archtecture of content addressable memory(CAM) for ASIC module generator. CAM is a special memory that is used to perform parallel data processing and data searching by virtue of the bit/word parallel searching and inexact matching capability. To adopt it in ASIC design, a new flexible architecture is required. We design a new flexible architecture specially suitable for module generator. The designed architecture supports various applications, i. e., cache memory,. TLB, image recognition, data encoding/decoding, router, etc. The major of design is expansibility and flexibility. New leaf cells and floor plans of expansibility and flexibility are illustrated with figures. The target process is 0.6㎜ TLM CMOS.