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A Comparison of Parallel Multipliers with Neuron MOS and CMOS Technologies
Hirose, Kei,Yasuura, Hiroto 대한전자공학회 1996 APCCAS:Asia Pacific Conference on Circuits And Sys Vol.1 No.1
We intend to obtain a fast and high-density logic circuit combining neuron MOS transistors (neuMOS), that was developed in Tohoku university, into a binary logic circuit. In this paper, we focus on basic arithmetic functional circuits, a full-adder and a multiplier, and make a comparison of the area and delay of the neuMOS circuits with conventional CMOS logic circuits. The results of physical design and SPICE simulation show that the area of a neuMOS multiplier with full-adders decreases to about 65% of the area of CMOS, and the delay of a neuMOS multiplier with (7,3) parallel counters decreases to about 70% of the delay of CMOS.