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N-Type Carbon-Nanotube MOSFET Device Profile Optimization for Very Large Scale Integration
Sun, Yanan,Kursun, Volkan The Korean Institute of Electrical and Electronic 2011 Transactions on Electrical and Electronic Material Vol.12 No.2
Carbon-nanotube metal oxide semiconductor field effect transistor (CN-MOSFET) is a promising future device candidate. The electrical characteristics of 16 nm N-type CN-MOSFETs are explored in this paper. The optimum N-type CN-MOSFET device profiles with different number of tubes are identified for achieving the highest on-state to off-state current ratio ($I_{on}/I_{off}$). The influence of substrate voltage on device performance is also investigated in this paper. Tradeoffs between subthreshold leakage current and overall switch quality are evaluated with different substrate bias voltages. Technology development guidelines for achieving high-speed, low-leakage, area efficient, and manufacturable carbon nanotube integrated circuits are provided.
N-Type Carbon-Nanotube MOSFET Device Profile Optimization for Very Large Scale Integration
Yanan Sun,Volkan Kursun 한국전기전자재료학회 2011 Transactions on Electrical and Electronic Material Vol.12 No.2
Carbon-nanotube metal oxide semiconductor field effect transistor (CN-MOSFET) is a promising future device candidate. The electrical characteristics of 16 nm N-type CN-MOSFETs are explored in this paper. The optimum N-type CN-MOSFET device profiles with different number of tubes are identified for achieving the highest on-state to off-state current ratio (I_(on)/I_(off)). The influence of substrate voltage on device performance is also investigated in this paper. Tradeoffs between subthreshold leakage current and overall switch quality are evaluated with different substrate bias voltages. Technology development guidelines for achieving high-speed, low-leakage, area efficient, and manufacturable carbon nanotube integrated circuits are provided.
FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability
Salahuddin, Shairfe Muhammad,Kursun, Volkan,Jiao, Hailong The Korean Institute of Electrical and Electronic 2015 Transactions on Electrical and Electronic Material Vol.16 No.6
Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.
FinFET SRAM Cells with Asymmetrical Bitline Access Transistors for Enhanced Read Stability
Shairfe Muhammad Salahuddin,Volkan Kursun,Hailong Jiao 한국전기전자재료학회 2015 Transactions on Electrical and Electronic Material Vol.16 No.6
Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.