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An On-Chip Network Fabric Supporting Coarse-Grained Processor Array
Phi-Hung Pham,Phuong Mau,Jungmoon Kim,Chulwoo Kim IEEE 2013 IEEE transactions on very large scale integration Vol.21 No.1
<P>Coarse grained arrays (CGAs) with run-time reconfigurability play an important role in accelerating reconfigurable computing applications. It is challenging to design on-chip communication networks (OCNs) for such CGAs with dynamic run-time reconfigurability whilst satisfying the tight budgets of power and area for an embedded system. This paper presents a silicon-proven design of a 64-PE circuit-switched OCN fabric with a dynamic path-setup scheme capable of supporting an embedded coarse-grained processor array. A proof-of-concept test chip fabricated in a 0.13 μm CMOS process occupies a silicon area of 23 mm<SUP>2</SUP> and consumes a peak power of 200 mW @ 128 MHz and 1.2 Vcc, at room temperature. The OCN overhead consumes 9.4% of the area and 18% of the power of the total chip. Experimental results and analysis show that the proposed OCN fabric with its dynamic path-setup is suitable for use in an embedded CGA supporting fast run-time reconfigurability.</P>
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Phi-Hung Pham,Jongsun Park,Phuong Mau,Chulwoo Kim IEEE 2012 IEEE transactions on very large scale integration Vol.20 No.2
<P>It is a challenging task in a network-on-chip to design an on-chip switch/router to dynamically support (hard) guaranteed throughput under very tight on-chip constraints of power, timing, area, and time-to-market. This paper presents the design and implementation of a novel pipeline circuit-switched switch to support guaranteed throughput. The proposed circuit-switched switch, based on a backtracking probing path setup, operates with a source-synchronous wave-pipeline approach. The switch can support a dead- and live-lock free dynamic path-setup scheme and can achieve high bandwidth and high area and energy efficiency. A silicon-proven prototype of a 16-bit-data 5-bidirectional-port switch in a four-metal-layer 0.18-μ m CMOS standard-cell technology can yield an aggregate data bandwidth of up to 73.84 Gb/s, while occupying only a modest area of 0.0315 mm<SUP>2</SUP>. The synthesizable implementation of the proposed switch also results in a cost-effective design, fast development time, and portability.</P>
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