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Design and Characterization of ESD Protection Devices for High-Speed I/O in Advanced SOI Technology
Shuqing Cao,Salman, A.A.,Jung-Hoon Chun,Beebe, S.G.,Pelella, M.M.,Dutton, R.W. IEEE 2010 IEEE transactions on electron devices Vol.57 No.3
<P>This paper focuses on the characterization, modeling, and design of electrostatic discharge (ESD) protection devices such as the gated diode, the bulk substrate diode, and the double-well field-effect diode (DWFED) in 45 nm silicon-on-insulator technology. ESD protection capabilities are investigated using very fast transmission line pulsing tests to predict a device's performance in charged device model (CDM) ESD events. Device capacitance, which is critical for high-speed input/output performance, is evaluated, and biasing schemes and processing techniques are proposed to reduce the parasitic capacitance during normal operating conditions. Technology computer-aided design simulations are used to interpret the physical effects. The implementation of devices for meeting CDM protection requirements is discussed. Evaluation results identify DWFED as a promising candidate for the pad-based local-clamping scheme.</P>