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Low Power Reconfiguration of Approximate Arithmetic Units Using Verilog HDL
Nithin Nagabasavanna,Nagaraju Chowdaiah 보안공학연구지원센터 2016 International Journal of Hybrid Information Techno Vol.9 No.9
Approximate computing is the theme that a system can let applications trade off accuracy for efficiency. It involves any technique where the system intentionally let on incorrectness to the application layer in order for conserving some resource. Floating point numbers i.e. approximate real number arithmetic to save space and time over arbitrary precession numerical representation. Approximate (APP) Computing is a technique of computation which ripostes less accuracy in results instead of an accurate output, which is enough for the desired application. The proposed work gives the basic allies on approximate computing based on arithmetic units using Verilog HDL. In dual mode operation, full adders and its types of adders resemble minimizing the power consumption and overall delay. Results show the great power saving efficiency and the 37mV and overall delay of 15.519ns.