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Fault-Aware Dual-Layer Adaptive Error Control Technique for NoC
Waqar Amin,Naveed Khan Baloch,Jawad Ali Khan,Muhammad Iram Baig 한국산학기술학회 2015 SmartCR Vol.5 No.6
The network-on-a-chip (NoC) appeared as a promising solution to handle the communications requirements of the multiprocessor system-on-a-chip (MPSoC). As the complexity of designs rises and the technology scales down into the deep-submicron domain, the probability of errors in the NoC components increases. Fault tolerance is a vital aspect in designing NoC architectures for future MPSoCs. This paper proposes an adaptive fault-tolerant technique that is a hybrid end-to-end and hop-to-hop, offering benefits of both error control schemes, and introduces a fault-aware adaptive selective hop-to-hop error correction scheme. The proposed technique ensures improvement in reliability by reducing the latency of the network in low transient–noise conditions.