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        Quantum Effects in CMOS Devices

        Keun-JeongLee,Ji-SunPark,HyungsoonShin 한국물리학회 2002 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.41 No.6

        A MOSFET device is scaled to the deep sub-micron region in advanced VLSI system technology. If the short-channel effect is to be reduced and the device performance maximized in such device, the oxide thickness should be reduced and the substrate doping should be increased. As a result, a potential well is formed at the Si/SiO2 interface, and a quantum eect occurs. In this work, a new simulator, which predicts the quantum and the poly-depletion eects in a MOSFET structure, is developed. Using a self-consistent method, this simulator accurately predicts the carrier distribution because the calculation of the potential in the inversion layer is improved. Using the developed simulator, we compare the quantum eects in NMOS and PMOS, and analyze the differences. The oxide thickness and the channel doping dependences of the quantum eect are analyzed, and their causes are investigated. Also, buried-channel and surface-channel devices are compared, and the dierences and causes of the dierences are analyzed.

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