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A high efficiency on‐chip reconfigurable Doherty power amplifier for LTE communication cells
Kumar, Rajesh,Kanuajia, Binod Kumar,Dwari, Santanu,Kumar, Sandeep,song, Hanjung John Wiley Sons, Inc. 2018 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS Vol.60 No.10
<P><B>Abstract</B></P><P>In this paper, a high efficiency on‐chip reconfigurable Doherty power amplifier (DPA) with proposed topology is proposed for LTE or 4G communication cells. The proposed DPA consists of input driver topology, hybrid coupler, asymmetric amplifiers, and 1:1 balun filtered network. The proposed input driver circuit provides wide amplified signal operation within range of 2.3GHz to 6GHz with flat gain of 33 dB. The amplified signal is unsteadily divided into two paths toward the carrier and the power amplifier by 90<SUP>0</SUP> hybrid couplers and demonstrates 27.6 dB and 28.3 dB of gain along with 83.2% and 84.5% of power added efficiency at average output power of 40 dBm. The high efficiency and almost flatness in gain stability of proposed DPA providing better solution in order to overcome the interference and the broadband issues for LTE communication cells. The balun‐filtered network is employed for combined the two outputs of carrier and peak amplifiers that provides more uniform desired band of operation in the frequency responses. The proposed DPA circuit are implemented and optimized by using advanced design RF simulator platform. The fabricated chip is made by using 0.13 μm GaN HEMT on Si‐Nitride monolithic microwave integrated circuit die process. The fabricated chip of DPA provides 85% of PAE with 28 dB gain which are made close agreement with simulation results. The size of chip is 2.8*1.2mm<SUP>2</SUP> which occupies less die area as compared to existing DPAs.</P>
Roy, G.M.,Kumar, S.,Kanuajia, B.K.,song, H. Mackintosh Publications] 2017 Microelectronics journal Vol.67 No.-
<P>This work concerns on CMOS based trans-impedance amplifier (TIA) where enhancing the bandwidth by using optimized on-chip T-network for biomedical diagnosis applications. The proposed TIA consists of inductive peaking components as an input stage, distributed amplifier with feedback loop as middle stage while output as T-network. The proposed TIA with T-network achieves much wide band operation within range of 4.8-19.6 GHz. As compared to conventional TIA, additional trans-impedance bandwidth of 1.4 GHz in the lower band while 9.1 GHz in higher band are able to achieve for the proposed design. The proposed architectures are implemented into ADS platform using commercial 65 nm TSMC process. With this proposed technique, TIA also succeeds lower bit error rate (BER) for high speed data transmission in optical receiver i.e. beneficial towards the biomedical diagnosis. Chip fabrication of proposed TIA consuming less power of 10.8 mW from the power supply of 1.6 V. Measured and simulated data exhibits a wide bandwidth operation with trans-impedance gain of 55dBOand made good correlation with each other. Moreover, experimental BER demonstrates less than 10-11 by providing pseudorandom bit sequence at 6-11 Gb/s within desired band of operation in TIA. The optimized on-chip T-network occupies only 10% of the whole chip area of 0.4 mm(2).</P>