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Dual Gate Single-Electron Transistors with a Recessed Channel and Underlapped Source/Drain Structure
Lee, Joung-Eob,Kim, Garam,Yun, Jang-Gn,Kang, Kwon-Chil,Lee, Jung-Han,Kim, Dae-Hwan,Lee, Jong-Ho,Shin, Hyungcheol,Park, Byung-Gook IOP Publishing 2010 Japanese journal of applied physics Vol.49 No.r11
Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer
LEE, Dong Seup,YANG, Hong-Seon,KANG, Kwon-Chil,LEE, Joung-Eob,LEE, Jung Han,CHO, Seongjae,PARK, Byung-Gook The Institute of Electronics, Information and Comm 2010 IEICE transactions on electronics Vol.93 No.5
<P>We propose a gate-all-around tunnel field effect transistor (GAA TFET) having a n-doped layer at the source junction and investigate its electrical characteristics with device simulation. By introducing the n-doped layer, band-to-band tunneling area is increased and tunneling barrier width is decreased. Also, electric field induced by gate bias is increased by the surrounding gate structure, which makes it possible to obtain a more abrupt band-bending. These effects bring about a significant improvement in on-current and subthreshold characteristics. GAA TFET with n-doped layer shows subthreshold swing at <I>I<SUB>d</SUB></I> =1nA/µm of 32.5mV/dec, average subthreshold swing of 20.6mV/dec. With comparison to other TFET structures, the merits of the proposed device are demonstrated and performance dependences on device parameters are characterized by extensive simulations.</P>
Fabrication and Characteristics of Self-Aligned Dual-Gate Single-Electron Transistors
Dong Seup Lee,Sangwoo Kang,Kwon-Chil Kang,Joung-Eob Lee,Jung Hoon Lee,Kwan-Jae Song,Dong Myong Kim,Jong Duk Lee,Byung-Gook Park IEEE 2009 IEEE TRANSACTIONS ON NANOTECHNOLOGY Vol.8 No.4
<P>Single-electron transistors that have electrical tunneling barriers are fabricated, and Coulomb oscillation peaks and negative differential transconductance are observed at room temperature (300 K). Operation characteristics and multioscillation peaks are further investigated at low temperature (80 K). The period of Coulomb oscillation is 2.3 V due to an ultrasmall control gate capacitance, and oscillation peaks are shifted through the side gate bias, which is explained by the derived stability plot for dual-gate structures. Even with the side gates electrically floating, the device still operates as a single-electron transistor since the p-n junction barrier plays a role of tunneling barrier. In addition, by changing the bias condition, double dots are formed along the channel and peak splitting is observed.</P>
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
PARK, Sang Hyuk,KANG, Sangwoo,CHO, Seongjae,LEE, Dong-Seup,LEE, Jung Han,YANG, Hong-Seon,KANG, Kwon-Chil,LEE, Joung-Eob,LEE, Jong Duk,PARK, Byung-Gook The Institute of Electronics, Information and Comm 2009 IEICE transactions on electronics Vol.92 No.5
<P>A Recessed-Channel Dual-Gate Single Electron Transistor (RCDG-SET) which has the possibility of room temperature operation is proposed. Side gates of a RCDG-SET form electrical tunneling barriers around a recessed channel, which is newly introduced. Not only gate but also a recessed channel is self aligned to source and drain. Characteristics of a RCDG-SET are compared with those of previous DG-SETs through device simulation (SILVACO). Due to a recessed channel and a self aligned structure, MOSFET current which causes low Peak-to-Valley Current Ratio (PVCR) is suppressed. This property of a RCDG-SET is expected to contribute for room temperature operation.</P>
Poly-silicon Quantum-dot Single-electron Transistors
Kwon-Chil Kang,Joung-Eob Lee,이정한,이종호,신형철,박병국 한국물리학회 2012 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.60 No.1
For operation of a single-electron transistors (SETs) at room temperature, we proposed a fabrication method for a SET with a self-aligned quantum dot by using polycrystalline silicon (poly-Si). The self-aligned quantum dot is formed by the selective etching of a silicon nanowire on a planarized surface and the subsequent deposition and etch-back of poly-silicon or chemical mechanical polishing (CMP). The two tunneling barriers of the SET are fabricated by thermal oxidation. Also,to decrease the leakage current and control the gate capacitance, we deposit a hard oxide mask layer. The control gate is formed by using an electron beam and photolithography on chemical vapor deposition (CVD). Owing to the small capacitance of the narrow control gate due to the tetraethyl orthosilicate (TEOS) hard mask, we observe clear Coulomb oscillation peaks and differential trans-conductance curves at room temperature. The clear oscillation period of the fabricated SET is 2.0 V. For operation of a single-electron transistors (SETs) at room temperature, we proposed a fabrication method for a SET with a self-aligned quantum dot by using polycrystalline silicon (poly-Si). The self-aligned quantum dot is formed by the selective etching of a silicon nanowire on a planarized surface and the subsequent deposition and etch-back of poly-silicon or chemical mechanical polishing (CMP). The two tunneling barriers of the SET are fabricated by thermal oxidation. Also,to decrease the leakage current and control the gate capacitance, we deposit a hard oxide mask layer. The control gate is formed by using an electron beam and photolithography on chemical vapor deposition (CVD). Owing to the small capacitance of the narrow control gate due to the tetraethyl orthosilicate (TEOS) hard mask, we observe clear Coulomb oscillation peaks and differential trans-conductance curves at room temperature. The clear oscillation period of the fabricated SET is 2.0 V.
Single-Crystalline Si STacked ARray (STAR) NAND Flash Memory
Jang-Gn Yun,Kim, Garam,Joung-Eob Lee,Yoon Kim,Won Bo Shim,Jong-Ho Lee,Hyungcheol Shin,Jong Duk Lee,Byung-Gook Park IEEE 2011 IEEE transactions on electron devices Vol.58 No.4
<P>In this paper, a 3-D NAND Flash memory array having multiple single-crystal Si nanowires is investigated. Device structure and fabrication process are described including the electrical isolation of stacked nanowires. Numerical simulation results focused on NAND Flash memory operation are delivered. Devices and array with stacked bit lines are fabricated, and memory characteristics such as program/erase select gate operation are measured. Array scheme is also discussed for the high-density bit-cost scalable 3-D stacked bit-line NAND Flash memory application.</P>