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Design of Low Power Signed Multiplier Based on EMBR Techniques
J. Venkata Suman,K. N. Narendra Swamy 보안공학연구지원센터 2015 International Journal of Hybrid Information Techno Vol.8 No.11
Multiplier is the major component for processing of large amount of data in DSP applications. Using different recoding schemes in Fused Add-Multiply (FAM) design for the reduction of power and look up tables. The performances of 8-bit, 12-bit & 16-bit signed multipliers were designed and obtained results are tabulated using Efficient Modified Booth Recoding (EMBR) techniques, which can be used for low power applications.
Design of 16-bit Multiplier Using Efficient Recoding Techniques
K. N. Narendra Swamy,J. Venkata Suman 보안공학연구지원센터 2015 International Journal of Hybrid Information Techno Vol.8 No.10
Multiplier is the major component for processing of large amount of data in DSP applications. Using different recoding schemes in Fused Add-Multiply (FAM) design for the reduction of power and look up tables. The performance of 16-bit signed and unsigned multipliers were designed and obtained results are tabulated using Efficient Modified Booth Recoding (EMBR) techniques, which can be used for low power applications.