Dual-Side Circulating Currents Free TPS Control for Dual Active Bridge DC-DC Converter and Its Implementation

Fengjiang Wu,Guizhong Wang,Xiaoguang Li 전력전자학회 2019 ICPE(ISPE)논문집 Vol.2019 No.5

In this paper, a novel triple phase-shift (NTPS) modulation is proposed first to eliminate the dual-side circulating currents of isolated dual-active bridge DC-DC converter. Furthermore, the current stress of the proposed NTPS control when the phase shift is tuned in two regions is derived and compared with each other and the best tuning region of the phase shift is determined to achieve the optimal current characteristics. The steady-state and transient performance of two implementation methods of NTPS control are discussed and the better one is determined. The corresponding experimental results of the proposed NTPS control validate its accuracy and validity.

Half-Cycle-Waveform-Inversed Single-Carrier Seven-level Sinusoidal Modulation

Wu, Fengjiang,Sun, Bo,Zhang, Lujie,Sun, Li The Korean Institute of Power Electronics 2013 JOURNAL OF POWER ELECTRONICS Vol.13 No.1

A half-cycle-waveform inversion based three reference modulations seven-level SPWM (TRM-SPWM) scheme with one carrier is proposed in this paper. To keep the same comparison logics for the modulations and carrier during the negative half cycle and the positive one for the modulations, in the negative half cycle of the modulations, the DC offsets related to the amplitude of the carrier are set on the three modulations, respectively. The seven-level SPWM waveform with dead time thereby is implemented with only one Digital Signal Processor (DSP) without any other attached logic circuit. The basis principle of the proposed TRM-SPWM is analyzed in detail, and the frequency spectrums of the conventional and the proposed schemes are derived and compared with each other through simulation. The DSP based implementation is presented and detailed experimental waveforms verify the accuracy and feasibility of the proposed TRM-SPWM scheme.

Half-Cycle-Waveform-Inversed Single-Carrier Seven-level Sinusoidal Modulation

Fengjiang Wu,Bo Sun,Lujie Zhang,Li Sun 전력전자학회 2013 JOURNAL OF POWER ELECTRONICS Vol.13 No.1

A half-cycle-waveform inversion based three reference modulations seven-level SPWM (TRM-SPWM) scheme with one carrier is proposed in this paper. To keep the same comparison logics for the modulations and carrier during the negative half cycle and the positive one for the modulations, in the negative half cycle of the modulations, the DC offsets related to the amplitude of the carrier are set on the three modulations, respectively. The seven-level SPWM waveform with dead time thereby is implemented with only one Digital Signal Processor (DSP) without any other attached logic circuit. The basis principle of the proposed TRM-SPWM is analyzed in detail, and the frequency spectrums of the conventional and the proposed schemes are derived and compared with each other through simulation. The DSP based implementation is presented and detailed experimental waveforms verify the accuracy and feasibility of the proposed TRM-SPWM scheme.

Elimination of the State-of-Charge Errors for Distributed Battery Energy Storage Devices in Islanded Droop-controlled Microgrids

Weixin Wang,Fengjiang Wu,Ke Zhao,Li Sun,Jiandong Duan,Dongyang Sun 전력전자학회 2015 JOURNAL OF POWER ELECTRONICS Vol.15 No.4

Battery energy storage devices (ESDs) have become more and more commonplace to maintain the stability of islanded power systems. Considering the limitation in inverter capacity and the requirement of flexibility in the ESD, the droop control was implemented in paralleled ESDs for higher capacity and autonomous operation. Under the conventional droop control, state-of-charge (SoC) errors between paralleled ESDs is inevitable in the discharging operation. Thus, some ESDs cease operation earlier than expected. This paper proposes an adaptive accelerating parameter to improve the performance of the SoC error eliminating droop controller under the constraints of a microgrid. The SoC of a battery ESD is employed in the active power droop coefficient, which could eliminate the SoC error during the discharging process. In addition, to expedite the process of SoC error elimination, an adaptive accelerating parameter is dedicated to weaken the adverse effect of the constraints due to the requirement of the system running. Moreover, the stability and feasibility of the proposed control strategy are confirmed by small-signal analysis. The effectiveness of the control scheme is validated by simulation and experiment results.

Elimination of the State-of-Charge Errors for Distributed Battery Energy Storage Devices in Islanded Droop-controlled Microgrids

Wang, Weixin,Wu, Fengjiang,Zhao, Ke,Sun, Li,Duan, Jiandong,Sun, Dongyang The Korean Institute of Power Electronics 2015 JOURNAL OF POWER ELECTRONICS Vol.15 No.4

Battery energy storage devices (ESDs) have become more and more commonplace to maintain the stability of islanded power systems. Considering the limitation in inverter capacity and the requirement of flexibility in the ESD, the droop control was implemented in paralleled ESDs for higher capacity and autonomous operation. Under the conventional droop control, state-of-charge (SoC) errors between paralleled ESDs is inevitable in the discharging operation. Thus, some ESDs cease operation earlier than expected. This paper proposes an adaptive accelerating parameter to improve the performance of the SoC error eliminating droop controller under the constraints of a microgrid. The SoC of a battery ESD is employed in the active power droop coefficient, which could eliminate the SoC error during the discharging process. In addition, to expedite the process of SoC error elimination, an adaptive accelerating parameter is dedicated to weaken the adverse effect of the constraints due to the requirement of the system running. Moreover, the stability and feasibility of the proposed control strategy are confirmed by small-signal analysis. The effectiveness of the control scheme is validated by simulation and experiment results.

A Flexible Five-level Cascaded H-bridge Inverter for Photovoltaic Gird-connected systems

Bo Sun,Fengjiang Wu,Mehdi Savaghebi,Josep M.Guerrero 전력전자학회 2015 ICPE(ISPE)논문집 Vol.2015 No.6

With the rapid penetration of photovoltaic (PV) grid-connected system in industrial and commercial application, it is critical to improve the efficiency and enhance the utilization of PV power generation system. This paper proposes a flexible five-level topology based on cascaded multi-level inverter for PV grid-connected system. By adding a bidirectional switch to conventional multi-level inverter, the proposed topology transforms operating mode between two-level H-bridge inverter (HBI) and cascaded multilevel inverter (CMI) according to the variation of DC link voltage. When output voltages of PV arrays are lower, the proposed inverter works in CMI mode to widen the generation range. When output voltages of PV panels are higher, inverter works in HBI mode to increase the efficiency. Hence the system incorporate the low losses feature of HBI and low grid-connected current THD advantages of CMI. This way, a wide range output voltage operation with high efficiency can be achieved without extra DC-DC converter. Experimental results of the proposed five-level CMI are presented to validate the feasibility of the proposed topology.

Effects of Input Harmonics, DC Offset and Step Changes of the Fundamental Component on Single-Phase EPLL and Elimination

Linsong Luo,Huixin Tian,Fengjiang Wu 전력전자학회 2015 JOURNAL OF POWER ELECTRONICS Vol.15 No.4

In this paper, the expressions of the estimated information of a single-phase enhanced phase-locked loop (EPLL), when input signal contains harmonics and a DC offset while the fundamental component takes step changes, are derived. The theoretical analysis results indicate that in the estimated information, the n<SUP>th</SUP>-order harmonics cause n+1th-order periodic ripples, and the DC offset causes a periodic ripple at the fundamental frequency. Step changes of the amplitude, phase angle and frequency of the fundamental component cause a transient periodic ripple at twice the frequency. These periodic ripples deteriorate the performance of the EPLL. A hybrid filter based EPLL (HF-EPLL) is proposed to eliminate these periodic ripples. A delay signal cancellation filter is set at the input of the EPLL to cancel the DC offset and even-order harmonics. A sliding Goertzel transform-based filter is introduced into the amplitude estimation loop and frequency estimation loop to eliminate the periodic ripples caused by the residual input odd-order harmonics and step change of the input fundamental component. The parameter design rules of the two filters are discussed in detail. Experimental waveforms of both the conventional EPLL and the proposed HF-EPLL are given and compared with each other to verify the theoretical analysis and advantages of the proposed HF-EPLL.

Effects of Input Harmonics, DC Offset and Step Changes of the Fundamental Component on Single-Phase EPLL and Elimination

Luo, Linsong,Tian, Huixin,Wu, Fengjiang The Korean Institute of Power Electronics 2015 JOURNAL OF POWER ELECTRONICS Vol.15 No.4

In this paper, the expressions of the estimated information of a single-phase enhanced phase-locked loop (EPLL), when input signal contains harmonics and a DC offset while the fundamental component takes step changes, are derived. The theoretical analysis results indicate that in the estimated information, the n^th-order harmonics cause n+1^th-order periodic ripples, and the DC offset causes a periodic ripple at the fundamental frequency. Step changes of the amplitude, phase angle and frequency of the fundamental component cause a transient periodic ripple at twice the frequency. These periodic ripples deteriorate the performance of the EPLL. A hybrid filter based EPLL (HF-EPLL) is proposed to eliminate these periodic ripples. A delay signal cancellation filter is set at the input of the EPLL to cancel the DC offset and even-order harmonics. A sliding Goertzel transform-based filter is introduced into the amplitude estimation loop and frequency estimation loop to eliminate the periodic ripples caused by the residual input odd-order harmonics and step change of the input fundamental component. The parameter design rules of the two filters are discussed in detail. Experimental waveforms of both the conventional EPLL and the proposed HF-EPLL are given and compared with each other to verify the theoretical analysis and advantages of the proposed HF-EPLL.

Improved virtual quadrature-coordinate EPLL considering input harmonics and DC offset

Yin, Dong,Wang, Guizhong,Wu, Fengjiang,Guo, Zhizhong The Korean Institute of Power Electronics 2020 JOURNAL OF POWER ELECTRONICS Vol.20 No.1

The two-phase quadrature-coordinate enhanced phase-locked loop (QC-EPLL) possesses a better transient performance than the standard single-phase EPLL. In this paper, a virtual QC-EPLL (VQC-EPLL) based on signal delay method is proposed to realize using QC-EPLL to estimate the synchronization information of the single-phase grid. Furthermore, the effect of the input harmonics and DC offset on the VQC-EPLL is originally derived and it reveals these nonideal conditions causes the unexpected periodical ripple in the estimated amplitude, phase angle and frequency. Furthermore, the improved approach, including the DC offset estimator and finite impulse response filter is proposed to eliminate these effect. Detailed experimental results verify the correctness and feasibility of the theoretical analysis and proposed improved approach.