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      • KCI등재

        TOPOLOGICAL ANALYSIS OF POWERTRAINS FOR REFUSECOLLECTING VEHICLES BASED ON REAL ROUTES – PART I: HYBRID HYDRAULIC POWERTRAIN

        F. SORIANO,M. MORENO-EGUILAZ,J. ALVAREZ,J. RIERA 한국자동차공학회 2016 International journal of automotive technology Vol.17 No.5

        In this two-part paper, a topological analysis of powertrains for refuse-collecting vehicles (RCVs) based on the simulation of different architectures (internal combustion engine, hybrid electric, and hybrid hydraulic) on real routes is proposed. In this first part, a characterization of a standard route is performed, analyzing the average power consumption and the most frequent working points of an internal combustion engine (ICE) in real routes. This information is used to define alternative powertrain architectures. A hybrid hydraulic powertrain architecture is proposed and modelled. The proposed powertrain model is executed using two different control algorithms, with and without predictive strategies, with data obtained from real routes. A calculation engine (an algorithm which runs the vehicle models on real routes), is presented and used for simulations. This calculation engine has been specifically designed to analyze if the different alternative powertrain delivers the same performance of the original ICE. Finally, the overall performance of the different architectures and control strategies are summarized into a fuel and energy consumption table, which will be used in the second part of this paper to compare with the different architectures based on hybrid electric powertrain. The overall performance of the different architectures indicates that the use of a hybrid hydraulic powertrain with simple control laws can reduce the fuel consumption up to a 14 %.

      • KCI등재

        TOPOLOGICAL ANALYSIS OF POWERTRAINS FOR REFUSECOLLECTING VEHICLES BASED ON REAL ROUTES – PART II: HYBRID ELECTRIC POWERTRAIN

        F. SORIANO,M. MORENO-EGUILAZ,J. ALVAREZ,J. RIERA 한국자동차공학회 2016 International journal of automotive technology Vol.17 No.5

        In this two-part paper, a topological analysis of powertrains for refuse-collecting vehicles (RCVs) based on simulation of different architectures (internal combustion engine, hybrid electric, and hybrid hydraulic) on real routes is proposed. In this second part, three different hybrid electric powertrain architectures are proposed and modeled. These architectures are based on the use of fuel cells, ultracapacitors, and batteries. A calculation engine, which is specifically designed to estimate energy consumption, respecting the original performance as the original internal combustion engine (ICE), is presented and used for simulations and component sizing. Finally, the overall performance of the different architectures (hybrid hydraulic, taken from the first paper part, and hybrid electric, estimated in this second part) and control strategies are summarized in a fuel and energy consumption table. Based on this table, an analysis of the different architecture performance results is carried out. From this analysis, a technological evolution of these vehicles in the medium- and long terms is proposed.

      • SCIESCOPUSKCI등재

        FPGA Based Robust Open Transistor Fault Diagnosis and Fault Tolerant Sliding Mode Control of Five-Phase PM Motor Drives

        Salehifar, Mehdi,Arashloo, Ramin Salehi,Eguilaz, Manuel Moreno,Sala, Vicent The Korean Institute of Power Electronics 2015 JOURNAL OF POWER ELECTRONICS Vol.15 No.1

        The voltage-source inverters (VSI) supplying a motor drive are prone to open transistor faults. To address this issue in fault-tolerant drives applicable to electric vehicles, a new open transistor fault diagnosis (FD) method is presented in this paper. According to the proposed method, in order to define the FD index, the phase angle of the converter output current is estimated by a simple trigonometric function. The proposed FD method is adaptable, simple, capable of detecting multiple open switch faults and robust to load operational variations. Keeping the FD in mind as a mandatory part of the fault tolerant control algorithm, the FD block is applied to a five-phase converter supplying a multiphase fault-tolerant PM motor drive with non-sinusoidal unbalanced current waveforms. To investigate the performance of the FD technique, the fault-tolerant sliding mode control (SMC) of a five-phase brushless direct current (BLDC) motor is developed in this paper with the embedded FD block. Once the theory is explained, experimental waveforms are obtained from a five-phase BLDC motor to show the effectiveness of the proposed FD method. The FD algorithm is implemented on a field programmable gate array (FPGA).

      • KCI등재

        FPGA Based Robust Open Transistor Fault Diagnosis and Fault Tolerant Sliding Mode Control of Five-Phase PM Motor Drives

        Mehdi Salehifar,Ramin Salehi Arashloo,Manuel Moreno Eguilaz,Vicent Sala 전력전자학회 2015 JOURNAL OF POWER ELECTRONICS Vol.15 No.1

        The voltage-source inverters (VSI) supplying a motor drive are prone to open transistor faults. To address this issue in faulttolerant drives applicable to electric vehicles, a new open transistor fault diagnosis (FD) method is presented in this paper. According to the proposed method, in order to define the FD index, the phase angle of the converter output current is estimated by a simple trigonometric function. The proposed FD method is adaptable, simple, capable of detecting multiple open switch faults and robust to load operational variations. Keeping the FD in mind as a mandatory part of the fault tolerant control algorithm, the FD block is applied to a five-phase converter supplying a multiphase fault-tolerant PM motor drive with nonsinusoidal unbalanced current waveforms. To investigate the performance of the FD technique, the fault-tolerant sliding mode control (SMC) of a five-phase brushless direct current (BLDC) motor is developed in this paper with the embedded FD block. Once the theory is explained, experimental waveforms are obtained from a five-phase BLDC motor to show the effectiveness of the proposed FD method. The FD algorithm is implemented on a field programmable gate array (FPGA).

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